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8T73S208 PDF даташит

Спецификация 8T73S208 изготовлена ​​​​«Integrated Device Technology» и имеет функцию, называемую «Differential LVPECL Clock Divider and Fanout Buffer».

Детали детали

Номер произв 8T73S208
Описание Differential LVPECL Clock Divider and Fanout Buffer
Производители Integrated Device Technology
логотип Integrated Device Technology логотип 

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8T73S208 Даташит, Описание, Даташиты
2.5 V, 3.3 V Differential LVPECL
Clock Divider and Fanout Buffer
8T73S208
Datasheet
General Description
The 8T73S208 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
The integrated input termination resistors make interfacing to the
reference source easy and reduce passive component count. Each
output can be individually enabled or disabled in the high-impedance
state controlled by a I2C register. On power-up, all outputs are
enabled.
Features
One differential input reference clock
Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVPECL outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1000MHz
LVCMOS interface levels for the control inputs
Individual output enable/disabled by I2C interface
Output skew: 15ps (typical)
Output rise/fall times: 350ps (maximum)
Low additive phase jitter, RMS: 0.182ps (typical)
Full 2.5V and 3.3V supply voltages
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0]
Pulldown (2)
2
SDA Pullup
I2C
SCL Pullup
8
ADR[1:0] Pulldown (2)
2
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
FSEL1
IN
VT
nIN
VCC
SDA
SCL
ADR0
24 23 22 21 20 19 18 17
25 16
26 15
27 14
28 13
8T73S208
29 12
30 11
31 10
32 9
12345678
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
Q7
nQ7 32-pin, 5mm x 5mm VFQFN
©2016 Integrated Device Technology, Inc.
1
Revision D, June 15, 2016









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8T73S208 Даташит, Описание, Даташиты
8T73S208 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
1,
32
ADR1, ADR0
Type
Input
Pulldown
Description
I2C Address inputs. LVCMOS/LVTTL interface levels.
2, 7, 18, 23
3, 4
5, 6
VEE
Q0, nQ0
Q1, nQ1
Power
Output
Output
Negative supply pins.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
8, 17
9, 10
11, 12
13, 14
15, 16
VCCO
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Power
Output
Output
Output
Output
Output supply pins.
Differential output pair 2. LVPECL interface levels.
Differential output pair 3. LVPECL interface levels.
Differential output pair 4. LVPECL interface levels.
Differential output pair 5. LVPECL interface levels.
19, 20
Q6, nQ6
Output
Differential output pair 6. LVPECL interface levels.
21, 22
24,
25
Q7, nQ7
FSEL0,
FSEL1
Output
Input
Pulldown
Differential output pair 7. LVPECL interface levels.
Frequency divider select controls. See Table 3A for function.
LVCMOS/LVTTL interface levels.
26 IN Input
27
VT
Termination
Input
Non-inverting differential clock input. RT = 50termination to VT.
Input for termination. Both IN and nIN inputs are internally terminated 50
to this pin. See input termination information in the applications section.
28 nIN Input
Inverting differential clock input. RT = 50termination to VT.
29 VCC Power
Power supply pin.
30
SDA
I/O
Pullup
I2C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output:
open drain.
31
SCL
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc.
2
Revision D, June 15, 2016









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8T73S208 Даташит, Описание, Даташиты
8T73S208 Datasheet
Function Tables
Input Frequency Divider Operation
The FSEL1 and FSEL0 control pins configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to
divide-by-2, 4 or 8, respectively.
Table 3A. FSEL[1:0] Input Selection Function Table
Input
FSEL1
FSEL0
0 (default) 0 (default)
01
10
11
Operation
fQ[7:0] = fREF ÷ 1
fQ[7:0] = fREF ÷ 2
fQ[7:0] = fREF ÷ 4
fQ[7:0] = fREF ÷ 8
NOTE: FSEL1, FSEL0 are asynchronous controls
Output Enable Operation
The output enable/disable state of each individual differential output
Qx, nQx can be set by the content of the I2C register (see Table 3C).
A logic zero to an I2C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I2C bits
(Dn) to its default state (logic 0) and all Qx, nQx outputs are enabled.
After the first valid I2C write, the output enable state is controlled by
the I2C register. Setting and changing the output enable state through
the I2C interface is asynchronous to the input reference clock.
The device supports the enable/disable of individual outputs.
During an active operation of the device, enabling individual
previously disabled outputs may degrade signal integrity of already
enabled active outputs during the enabling transition. Disabling
multiple outputs is supported without signal integrity constraints.
Table 3B. Individual Output Enable Control
Bit
Dn
0 (default)
1
Operation
Output Qx, nQx is enabled.
Output Qx, nQx is disabled in high-impedance
state.
Table 3C. Individual output enable control
Bit D7 D6 D5 D4 D3 D2 D1 D0
Output Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Default 0 0 0 0 0 0 0 0
I2C Interface Protocol
The IDT8T73S208I uses an I2C slave interface for writing and
reading the device configuration to and from the on-chip
configuration registers. This device uses the standard I2C write
format for a write transaction, and a standard I2C read format for a
read transaction. Figure 1 defines the I2C elements of the standard
I2C transaction. These elements consist of a start bit, data bytes, an
acknowledge or Not-Acknowledge bit and the stop bit. These
elements are arranged to make up the complete I2C transactions as
shown in Figure 2 and Figure 3. Figure 2 is a write transaction while
Figure 3 is read transaction. The 7-bit I2C slave address of the
8T73S208 is a combination of a 4-bit fixed addresses and two
variable bits which are set by the hardware pins ADR[1:0] (binary
11010, ADR1, ADR0). Bit 0 of slave address is used by the bus
controller to select either the read or write mode. The hardware pins
ADR1 and ADR0 and should be individually set by the user to avoid
address conflicts of multiple 8T73S208 devices on the same bus.
Table 3D. I2C Slave Address
76543210
1 1 0 1 0 ADR1 ADR0 R/W
SCL
SDA
START
Valid Data
Acknowledge
Figure 1: Standard I2C Transaction
STOP
START (S) – defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA – between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (A) – SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
STOP (S) – defined as low-to-high transition on SDA while holding
SCL HIGH
S DevAdd W A Data Byte A P
Figure 2: Write Transaction
S DevAdd R A Data Byte
Figure 3: Read Transaction
AP
S
W
R
A
DevAdd
P
Start or Repeated Start
R/~W is set for Write
R/~W is set for Read
Ack
7 bit Device Address
Stop
©2016 Integrated Device Technology, Inc.
3
Revision D, June 15, 2016










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