8T49N4811 PDF даташит
Спецификация 8T49N4811 изготовлена «Integrated Device Technology» и имеет функцию, называемую «I2C Programmable Ethernet Clock Generator». |
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Детали детали
Номер произв | 8T49N4811 |
Описание | I2C Programmable Ethernet Clock Generator |
Производители | Integrated Device Technology |
логотип |
30 Pages
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I2C Programmable Ethernet Clock
Generator
8T49N4811
DATA SHEET
General Description
The 8T49N4811I is a highly flexible FemtoClock® NG
pin-programmable clock generator suitable for networking and
communications applications. It is able to generate five different
output frequencies with multiple copies of each. A fundamental mode
crystal, single-ended, or differential input reference may be used as
the source for the output frequency.
The use of pin-programming to select the input source / frequency,
desired output frequencies and output styles allow a single device to
be used in a wide variety of applications without the need for register
programming.
Selection pins use 3-level options to maximize flexibility while
minimizing package size. Selection is performed by tying a selection
pin high or low or by leaving it floating, eliminating the need for
passive components to drive a desired logic level.
Features
• Fourth generation FemtoClock® NG technology
• Generates multiple copies of 25MHz, 50MHz, 100MHz, 125MHz,
156.25MHz or 312.5MHz
• Typical input frequency is 25MHz, with optional 125MHz and
156.25MHz input support
• Differential outputs are pin programmable for LVDS or LVPECL
• RMS phase jitter at 156.25MHz: <300fs typical
• Power Supply Rejection Ratio better than -50dBc from
10k-1.5MHz at 3.3V power supply
• Full 3.3V and 2.5V Supply Voltages
• -40°C to +85°C ambient operating temperature
• 56-pin VFQFPN, lead-free (RoHS 6) packaging
Block Diagram
2.5V ±5% or 3.3V ±10%
PLL Bypass
SDATA, SCLK
IIC_ADRX_SEL
IN_SEL
XTAL_IN
fIN XTAL_OUT
DIN
nDIN
SLEW_LVCMOS
LVCMOS_CTRL
Qx_CTRL
QB_CTRL [1:0]
INPUT_DIVSEL
DIVSEL_x
100Ω
3
4
/A 0
1
OSC 0
1
fIN APLL
/B 0
1
/C 0
1
/D0
Frequency,
Output Type,
Slew Rate, &
Output Enable
Control
Input Divider
Frequency Select
/D1
Output Enable,Type, & Slew Rate Control
Bank A 1 LVPECL/LVDS
125MHz/156.25MHz/312.5MHz
Bank B 6 LVPECL/LVDS
50MHz/125MHz/156.25MHz
Bank C 2 LVPECL/LVDS
100MHz/125MHz/156.25MHz
Bank D0 1 LVPECL/LVDS
25MHz/125MHz/156.25MHz
Bank D1 1 LVCMOS
25MHz/125MHz
8T49N4811 REVISION A 3/30/15
1 ©2015 Integrated Device Technology, Inc.
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8T49N4811 DATA SHEET
Pin Assignment
QB_CTRL0
VDD
QA_CTRL
VDD_OA
nQA0
QA0
DIVSEL_A
QC_CTRL
VDD_OC
nQC1
QC1
nQC0
QC0
VDD_OC
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43 28
44 27
45 IDT8T49N4811I 26
46 25
47 56-Lead VFQFN 24
48 8mm x 8mm x 0.90mm 23
49 Package Body 22
50 5.9mm x 5.9mm ePad Size 21
51 NLG Suffix 20
52 Top View 19
53 18
54 17
55 16
56 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SLEW_LVCMOS
VDD
QB_CTRL1
VDD_OD
QD0
nQD0
QD_CTRL
VDD_ODS
QD0_S
nc
DIVSEL_B
Reserved
SDATA
SCLK
I2C PROGRAMMABLE ETHERNET CLOCK GENERATOR
2
REVISION A 3/30/15
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8T49N4811 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Description
Number
1
2
3
4
5
6
7
8
Name
DIVSEL_C
VDD
IN_SEL
DIN
nDIN
VDD_XTAL
XTAL_IN
XTAL_OUT
9 PLL_BYPASS
10 IIC_ADRX_SEL
11 VDDA
12 INPUT_DIVSEL
13 DIVSEL_D0
14 LVCMOS_CTRL
15 SCLK
16 SDATA
17 Reserved
18 DIVSEL_B
19 nc
20 QD0_S
21 VDD_ODS
22 QD_CTRL
23 nQD0
24 QD0
25 VDD_OD
26 QB_CTRL1
27 VDD
28 SLEW_LVCMOS
29 nQB5
30 QB5
31 nQB4
32 QB4
33 VDD_OB
34 nQB3
Type
Description
Input Pullup/Pulldown Output divider selection for Bank C. LVCMOS interface levels.
Power
Core supply.
Input Pullup/Pulldown Input select between XTAL or differential input. LVCMOS interface levels.
Input
Input
Power
Differential Reference Input. Accepts DC-coupled LVDS and is internally biased to
accept AC-coupled LVPECL, CML, HCSL or LVPECL signals. The differential
inputs have an internal 100 resistor biased to VDD–1.3V approximately.
Crystal oscillator power supply.
Input
Crystal input.
Output
Crystal output.
Input
Input
Pulldown
Pulldown
PLL Bypass. Provides copy of fIN to output banks A, B, C. LVCMOS interface
levels.
Selects between I2C addresses. LVCMOS interface levels.
Power
Analog supply.
Input
Pullup/Pulldown
Selects proper divide ratios for differential reference input. LVCMOS interface
levels.
Input Pullup/Pulldown Output divider selection for Bank D0 differential output. LVCMOS interface levels.
Input
Input
I/O
Pullup/Pulldown
Divider and output enable control for Bank D1 LVCMOS output. LVCMOS
interface levels.
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
Pullup I2C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output: Open Drain.
Pulldown Reserved. Internally connected to 50k pulldown.
Input Pullup/Pulldown Output divider selection for Bank B. LVCMOS interface levels.
This pin is not internally connected. Connect to ground to maintain second source
compatibility.
Output
Bank D1 LVCMOS Output.
Power
Power supply for Bank D1 LVCMOS output.
Input Pullup/Pulldown Control input for bank D0 output type and OE status. LVCMOS interface levels.
Output
Bank D0 Differential Output. LVDS or LVPECL output levels.
Output
Bank D0 Differential Output. LVDS or LVPECL output levels.
Power
Power supply for Bank D0 differential output.
Input
Pullup/Pulldown
Control input for bank B outputs QB3 to QB5 output type and OE status. LVCMOS
interface levels.
Power
Power supply.
Input
Pulldown Slew rate control pin for LVCMOS output. LVCMOS interface levels.
Output
Bank B Differential Output. LVDS or LVPECL output levels.
Output
Bank B Differential Output. LVDS or LVPECL output levels.
Output
Bank B Differential Output. LVDS or LVPECL output levels.
Output
Bank B Differential Output. LVDS or LVPECL output levels.
Power
Power supply for Bank B.
Output
Bank B Differential Output. LVDS or LVPECL output levels.
REVISION A 3/30/15
3 I2C PROGRAMMABLE ETHERNET CLOCK GENERATOR
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Номер в каталоге | Описание | Производители |
8T49N4811 | I2C Programmable Ethernet Clock Generator | Integrated Device Technology |
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