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Número de pieza | NB6L295M | |
Descripción | 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! NB6L295M
2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential CML
Outputs
Multi−Level Inputs w/ Internal Termination
The NB6L295M is a Dual Channel Programmable Delay Chip
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designed primarily for Clock or Data de−skewing and timing
adjustment. The NB6L295M is versatile in that two individual
variable delay channels, PD0 and PD1, can be configured in one of
MARKING
DIAGRAM*
two operating modes, a Dual Delay or an Extended Delay.
24
In the Dual Delay Mode, each channel has a programmable delay
section which is designed using a matrix of gates and a chain of
multiplexers. There is a fixed minimum delay of 3.2 ns per channel.
24 1
QFN−24
MN SUFFIX
CASE 485L
1
NB6L
295M
ALYWG
The Extended Delay Mode amounts to the additive delay of PD0
plus PD1 and is accomplished with the Serial Data Interface MSEL bit
set High. This will internally cascade the output of PD0 into the input
of PD1. Therefore, the Extended Delay path starts at the IN0/IN0
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G
inputs, flows through PD0, cascades to the PD1 and outputs through
G = Pb−Free Package
Q1/Q1. There is a fixed minimum delay of 6.0 ns for the Extended
(Note: Microdot may be in either location)
Delay Mode.
The required delay is accomplished by programming each delay
*For additional marking information, refer to
Application Note AND8002/D.
channel via a 3−pin Serial Data Interface, described in the application
ORDERING INFORMATION
section. The digitally selectable delay has an increment resolution of
See detailed ordering and shipping information in the package
typically 11 ps with a net programmable delay range of either 0 ns to
dimensions section on page 12 of this data sheet.
6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the
Extended Delay Mode.
The Multi−Level Inputs can be driven directly by differential
LVPECL, LVDS or CML logic levels; or by single ended LVPECL,
LVCMOS or LVTTL. A single enable pin is available to control both
inputs. The SDI input pins are controlled by LVCMOS or LVTTL
level signals. The NB6L295M 16 mA CML output contains
temperature compensation circuitry. This device is offered in a 4 mm x
4 mm 24−pin QFN Pb−free package. The NB6L295M is a member of
the ECLinPS MAX™ family of high performance products.
Features
• 2.4 ps Typical Clock Jitter, RMS
• Input Clock Frequency > 1.5 GHz with 210 mV
VOUTPP
• Input Data Rate > 2.5 Gb/s
• Programmable Delay Range: 0 ns to 6 ns per Delay
Channel
• Programmable Delay Range: 0 ns to 11.2 ns for
Extended Delay Mode
• Total Delay Range: 3.2 ns to 8.5 ns per Delay Channel
• Total Delay Range: 6.2 ns to 16.6 ns in Extended Delay
Mode
• Monotonic Delay: 11 ps Increments in 511 Steps
• Linearity $20 ps, Maximum
• 100 ps Typical Rise and Fall Times
• 20 ps Pk−Pk Typical Data Dependent Jitter
• LVPECL, CML or LVDS Differential Input Compatible
• LVPECL, LVCMOS, LVTTL Single Ended Input
Compatible
• 3−Wire Serial Interface
• Input Enable/Disable
• Operating Range: VCC = 2.375 V to 3.6 V
• CML Output Level; 380 mV Peak−to−Peak, Typical
• Internal 50 W Input/Output Termination Provided
• −40°C to 85°C Ambient Operating Temperature
• 24−Pin QFN, 4 mm x 4 mm
• These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 5
1
Publication Order Number:
NB6L295M/D
1 page NB6L295M
Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS VCC = VCC0 = VCC1 = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to
+85°C
Symbol
Characteristic
Min Typ Max Unit
POWER SUPPLY CURRENT
ICC Power Supply Current (Inputs, VTX and Outputs Open) (Sum of ICC,
ICC0, and ICC1)
CML OUTPUTS (Notes 5 and 6, Figure 22)
170 215 mA
VOH Output HIGH Voltage
VCC = VCC0 = VCC1 = 3.3 V
VCC = VCC0 = VCC1 = 2.5 V
VCC − 40
3260
2460
VOL Output LOW Voltage
VCC = VCC0 = VCC1 = 3.3 V
VCC = VCC0 = VCC1 = 2.5 V
VCC − 500
2800
2000
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 11 and 12) (Note 7)
VCC − 10
3290
2490
VCC − 400
2900
2100
VCC
3300
2500
VCC − 300
3000
2200
mV
mV
Vth Input Threshold Reference Voltage Range
1050
VIH Single−Ended Input HIGH Voltage
Vth +150
VIL Single−Ended Input LOW Voltage
GND
VISE
Single−Ended Input Voltage Amplitude (VIH − VIL)
300
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 13 and 14) (Note 8)
VCC − 150
VCC
Vth − 150
VCC − GND
mV
mV
mV
mV
VIHD
Differential Input HIGH Voltage
VILD
Differential Input LOW Voltage
VID Differential Input Voltage Swing (INx, INx) (VIHD − VILD)
VCMR Input Common Mode Range (Differential Configuration) (Note 9)
IIH Input HIGH Current INx/INX, (VTn/VTn Open)
IIL Input LOW Current IN/INX, (VTn/VTn Open)
SINGLE−ENDED LVCMOS/LVTTL CONTROL INPUTS
1200
GND
150
950
−150
−150
VCC
VCC − 150
VCC − GND
VCC – 75
150
150
mV
mV
mV
mV
mA
mA
VIH Single−Ended Input HIGH Voltage
VIL Single−Ended Input LOW Voltage
IIH Input HIGH Current
IIL Input LOW Current
TERMINATION RESISTORS
2000
GND
−150
−150
VCC
mV
800 mV
150 mA
150 mA
RTIN
RTOUT
Internal Input Termination Resistor
Internal Output Termination Resistor
40 50
40 50
60 W
60 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. CML outputs loaded with 50 W to VCC for proper operation.
6. Input and output parameters vary 1:1 with VCC.
7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. Vth is applied to the complementary input when operating in
single−ended mode.
8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
9. VCMR(min) varies 1:1 with voltage on GND pin, VCMR(max) varies 1:1 with VCC. The VCMR range is referenced to the most positive side of
the differential input signal.
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5
5 Page NB6L295M
VCC
VCC
VCC
VCC
LVPECL
Driver
INx
Zo = 50 W
VTx
VTx
NB6L295M
50 W
50 W
Zo = 50 W
INx
GND
VTx = VTx = VCC − 2.0 V
GND
Figure 17. LVPECL Interface
VCC
LVDS
Driver
INx
Zo = 50 W
VTx
VTx
Zo = 50 W
VTx = VTx INx
NB6L295M
50 W*
50 W*
GND
GND
Figure 18. LVDS Interface
VCC
CML
Driver
GND
INx
Zo = 50 W
VTx
VCC
VTx
Zo = 50 W
INx
VTx = VTx = VCC
NB6L295M
50 W*
50 W*
GND
Figure 19. CML Interface, Standard 50 W Load
VCC
VCC
VCC
VCC
Differential
Driver
INx
Zo = 50 W
VTx
VREFAC
VTx
NB6L295M
50 W*
50 W*
Zo = 50 W
INx
VTx = VTx = External VREFAC
GND
GND
Figure 20. Capacitor−Coupled Differential
Interface (VTx/VTx Connected to VREFAC;
VREFAC Bypassed to Ground with 0.1 mF
Capacitor)
Single−Ended
Driver
INx
Zo = 50 W
VTx
VREFAC
VTx
NB6L295M
50 W*
50 W*
INx
VTx = VTx = External VREFAC
GND
GND
Figure 21. Capacitor−Coupled Single−Ended
Interface (VTx/VTx Connected to External VREFAC;
VREFAC Bypassed to Ground with 0.1 mF Capacitor)
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11
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet NB6L295M.PDF ] |
Número de pieza | Descripción | Fabricantes |
NB6L295 | 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay | ON Semiconductor |
NB6L295M | 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay | ON Semiconductor |
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