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PDF 74LVC157A-Q100 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC157A-Q100 | |
| Descripción | Quad 2-input multiplexer | |
| Fabricantes | NXP Semiconductors | |
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74LVC157A-Q100
Quad 2-input multiplexer
Rev. 2 — 2 May 2013
Product data sheet
1. General description
The 74LVC157A-Q100 is a quad 2-input multiplexer which select four bits of data from two
sources under the control of a common select input (S). The four outputs present the
selected data in the true (non-inverted) form. The enable input (E) is active LOW. When
pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other
input conditions. Moving the data from two groups of registers to four common output
buses is a common use of the 74LVC157A-Q100. The state of the common data select
input (S) determines the particular register from which the data comes. It can also be used
as function generator.
It is useful for implementing highly irregular logic by generating any 4 of the 16 different
functions of two variables with one variable common.
The device is the logic implementation of a 4-pole, 2-position switch, where the position of
the switch is determined by the logic levels applied to pin S.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
1 page  
NXP Semiconductors
74LVC157A-Q100
Quad 2-input multiplexer
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK
input clamping current
VI < 0
VI input voltage
IOK
output clamping current
VO > VCC or VO < 0
VO output voltage
IO output current
VO = 0 V to VCC
0.5
50
[1] 0.5
-
[2] 0.5
-
+6.5
-
+6.5
50
VCC + 0.5
50
V
mA
V
mA
V
mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +125 C
-
100
65
[3] -
100
-
+150
500
mA
mA
C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO16 packages: above 70 C the value of PD derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 C the value of PD derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of PD derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC
VI
VO
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall
rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
Min Typ
1.65 -
1.2 -
0-
0-
40 -
0-
0-
Max
3.6
-
5.5
VCC
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
74LVC157A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
74LVC157A-Q100
Quad 2-input multiplexer
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
y
Z
16 9
c
EA
X
HE v M A
pin 1 index
1
e
8
bp
wM
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1) E (1)
e
HE
L
Lp
Q
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
v w y Z (1)
0.2
0.13
0.1
1.00
0.55
θ
8o
0o
OUTLINE
VERSION
SOT338-1
IEC
REFERENCES
JEDEC
JEITA
MO-150
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 11. Package outline SOT338-1 (SSOP16)
74LVC157A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 May 2013
© NXP B.V. 2013. All rights reserved.
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