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S6E2DH5J0A PDF даташит

Спецификация S6E2DH5J0A изготовлена ​​​​«Cypress Semiconductor» и имеет функцию, называемую «Microcontroller».

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Номер произв S6E2DH5J0A
Описание Microcontroller
Производители Cypress Semiconductor
логотип Cypress Semiconductor логотип 

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S6E2DH5J0A Даташит, Описание, Даташиты
S6E2DH Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the S6E2DH Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series
is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as
graphics engine, display controller, motor control timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products that are described in this data sheet are TYPE4-M4 category products. See the FM4 Family Peripheral Manual Main
Part (002-04856).
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 160 MHz frequency operation
Built-in FPU
Supports DSP instructions
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit system timer (Sys Tick): System timer for OS task
management
On-Chip Memories
Flash memory
This series has on-chip flash memory with these features:
384 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
Security function for code protection
Notes:
The read access to flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to flash memory can be obtained by
Flash Accelerator System.
SRAM
This is composed of two independent SRAMs (SRAM0 and
SRAM2). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M4F core. SRAM2 is connected to the system bus of
Cortex-M4F core.
SRAM0: 32 Kbytes
SRAM2: 4 Kbytes
VRAM
This series is equipped with a SRAM for GDC.
Max 512 Kbytes
VFLASH
S6E2DH5GJA is equipped with a Flash for GDC.
2 Mbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash and SDRAM devices
Up to two chip selects CS0 and CS8 (CS8 is only for
SDRAM)
8-/16-bit data width
Up to 25-bit address bit
Maximum area size : Up to 256 Mbytes
Supports address/data multiplexing
Supports external RDY function
Supports the scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0x7FFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key.
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
USB Interface (One channel)
A USB interface is composed of device and host.
USB device
USB2.0 Full-Speed supported
Max 6 EndPoint supported
EndPoint 0 is for control transfer
EndPoint 1, 2 can be selected for bulk-transfer,
interrupt-transfer or isochronous-transfer
EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
EndPoint 1 to 5 comprise the double buffer
The size of each endpoint is as follows.
Endpoint 0, 2 to 5: 64 bytes
EndPoint 1: 256 bytes
USB host
USB2.0 Full-Speed / Low-Speed supported
Bulk-transfer, interrupt-transfer and isochronous-transfer
support
USB device connected/disconnected automatically detect
In/out token handshake packet automatically accepted
Max 256-byte packet-length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-05038 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised March 4, 2016









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S6E2DH5J0A Даташит, Описание, Даташиты
S6E2DH Series
CAN-FD Interface (One channel)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 5 Mbps
Message buffer for receiver: Up to 192 messages
Message buffer for transmitter: Up to 32 messages
CAN with flexible data rate (non-ISO CAN FD)
Notes:
CAN FD cannot communicate between non-ISO CAN FD
and ISO CAN FD, because non-ISO CAN FD and ISO
CAN FD are different frame format.
About the problem of "non-ISO CAN FD", see the White
Paper from CiA(CAN in Automation).
http://www.can-newsletter.org/engineering/standardization/
141222_can-fd-and-crc-issued_white-paper_bosch
Multi-function Serial Interface (Max eight channels)
64 bytes with FIFO (the FIFO step numbers vary depending
on the settings of the communication mode or bit length.)
Operation mode is selectable from the following for each
channel.
UART
CSIO
LIN
I2C
UART
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detect functions available (parity errors,
framing errors, and overrun errors)
CSIO
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 and ch.7 only)
Supports High-speed SPI (ch.6 only)
Data length 5 to 16-bit
LIN
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can change to 13 to 16-bit
length)
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
I2C
Standard mode (Max 100 kbps) / Fast mode (Max 400
kbps) supported
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.4=ch.A)
supported
Document Number: 002-05038 Rev.*A
DMA Controller (Eight channels)
The DMA controller has an independent bus for the CPU, so
the CPU and the DMA controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or requested from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
DSTC (Descriptor System Data Transfer Controller)
(128 channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the descriptor system and,
following the specified contents of the descriptor that has
already been constructed on the memory, can directly access
the memory/peripheral device and performs the data transfer
operation.
It supports the software activation, the hardware activation,
and the chain activation functions.
A/D Converter (Max 24 channels)
12-bit A/D Converter
Successive Approximation type
Built-in 2 units
Conversion time: 1.0 μs @ 3.3 V
Priority conversion available (priority at two levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for priority conversion: four steps)
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set to which I/O port the
peripheral function can be allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in port relocate function
Up to 98 general-purpose I/O ports @ 120-pin package
Some I/O pins are 5V tolerant.
See "4. Pin Descriptions" and "5. I/O Circuit Type" for the
corresponding pins.
Page 2 of 183









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S6E2DH5J0A Даташит, Описание, Даташиты
S6E2DH Series
Multi-Function Timer (One unit)
The multi-function timer is composed of the following blocks.
Minimum resolution : 6.25 ns
16-bit free-run timer × 3ch.
Input capture × 4ch.
Output compare × 6ch.
A/D activation compare × 6ch.
Waveform generator × 3ch.
16-bit PPG timer × 3ch.
The following functions can be used to achieve motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D converter activate function
DTIF (motor emergency stop) interrupt function
Real-Time Clock (RTC)
The real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
01 to 99.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute/Second/A day of the week.) is
available. This function is also available by specifying only
Year, Month, Day, Hour or Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC)
(One channel)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The dual timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Document Number: 002-05038 Rev.*A
Watch Counter
The watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in High-speed CR clock or built-in Low-speed CR
clock as the clock source.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a hardware
watchdog and a software watchdog.
The hardware watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, the hardware watchdog is active in
any power saving mode except RTC mode and stop mode.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps verify data transmission or storage
integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
PRGCRC (Programmable Cyclic Redundancy
Check) Accelerator
The CRC accelerator helps verify data transmission or storage
integrity.
CCITT CRC16, IEEE-802.3 CRC32 and a generating
polynominal are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Generating polynominal
SD Card Interface
It is possible to use the SD card that conforms to the following
standards.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
3.00
1-bit or 4-bit data bus
Page 3 of 183










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S6E2DH5J0AMicrocontrollerCypress Semiconductor
Cypress Semiconductor

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