S6E2CC9HHA Datasheet PDF - Cypress Semiconductor
| Part Number | S6E2CC9HHA | |
| Description | Microcontroller | |
| Manufacturers | Cypress Semiconductor | |
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There is a preview and S6E2CC9HHA download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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S6E2CC Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the S6E2CC Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This
series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as
motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I2C, LIN). The products that
are described in this data sheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part
(002-04856)."
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 200 MHz frequency operation
FPU built-in
Support DSP instructions
Memory protection unit (MPU): improves the reliability of an
embedded system
Integrated nested vectored interrupt controller (NVIC): 1 NMI
(non-maskable interrupt) and 128 peripheral interrupts and
16 priority levels
24-bit system timer (Sys Tick): system timer for OS task
management
External Bus Interface
Supports SRAM, NOR, NAND flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-/32-bit data width
Up to 25-bit address bus
Supports address/data multiplexing
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key
Note: It is necessary to use the Cypress provided software
library to use the scramble function.
On-chip Memories
Flash memory
This series is based on two independent on-chip flash
memories.
Up to 2048 Kbytes
Built-in flash accelerator system with 16 Kbytes trace buffer
memory
Read access to flash memory that can be achieved without
wait-cycle up to an operating frequency of 72 MHz. Even at
the operating frequency more than 72 MHz, an equivalent
single cycle access to flash memory can be obtained by
the flash accelerator system.
Security function for code protection
SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to the I-code bus
and D-code bus of Cortex-M4F core. SRAM1 and SRAM2
are connected to system bus of Cortex-M4F core.
SRAM0: up to 192 Kbytes
SRAM1: 32 Kbytes
SRAM2: 32 Kbytes
USB Interface (Max two channels)
The USB interface is composed of a function and a host.
USB function
USB 2.0 Full-speed supported
Max 6 EndPoint supported
• EndPoint 0 is control transfer
• EndPoint 1, 2 can be selected bulk-transfer,
interrupt-transfer or isochronous-transfer
• EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
• EndPoint 1 to 5 comprise double buffer
• The size of each endpoint is as follows.
− Endpoint 0, 2 to 5: 64 byte
• EndPoint 1: 256 byte
USB host
USB2.0 Full-Speed/Low-Speed supported
Bulk-transfer, interrupt-transfer, and isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-04980 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised February 5, 2016
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S6E2CC Series
Clock and Reset
Clocks
Five clock sources (two external oscillators, two internal CR
oscillators, and Main PLL) that are dynamically selectable.
Main clock: 4 MHz to 48 MHz
Sub clock: 30 kHz to 100 kHz
High-speed internal CR clock: 4 MHz
Low-speed internal CR clock: 100 kHz
Main PLL Clock
Resets
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timer reset
Low-voltage detector reset
Clock supervisor reset
Clock Supervisor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include two-stage monitoring of voltage on the
VCC pins. When the voltage falls below the voltage that has
been set, the low-voltage detector function generates an
interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-power Consumption mode
Six low power consumption modes are supported.
Sleep
Timer
RTC
Stop
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby stop (selectable from with/without RAM
retention)
Peripheral Clock Gating
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral
functions not used.
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
RTC
32-kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
Crypto Assist Function
These features are enabled for the crypto assist function.
The dedicated middleware is necessary for this calculator
operation.
PKA (Public Key Accelerator)
PKA（Public Key Accelerator）is modular exponentiation
calculation accelerator used of RSA Public Key crypto and
so on.
Available bit length: Up to 2048-bit
AES calculator
AES (Advanced Encryption Standard) calculator is a AES
common key crypto accelerator which is compliant with
FIPS (Federal Information Processing Standard
Publication) 197.
Available key length: 128/192/256-bit
CBC mode and ECB mode support
SHA-256 calculator
SHA-256 calculator is a SHA-256 hash function
accelerator which is compliant with FIPS180-2.
External Bus Data Scramble
It enables to scramble input/output data of External Bus
Interface.
Voice Function
These features are enabled for the voice function.
The dedicated library is necessary for using the voice
function.
Automatic Speech Recognition (ASR)
100 custom commands in multiple languages
User commands defined with a text file (no audio input or
training required)
Natural Language Understanding (NLU)
Document Number: 002-04980 Rev.*A
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