PDF 8P34S2106 Data sheet ( Hoja de datos )

Número de pieza	8P34S2106
Descripción	Dual 1:6 LVDS Output 1.8V Fanout Buffer
Fabricantes	IDT
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No Preview Available ! Dual 1:6 LVDS Output 1.8V Fanout Buffer 8P34S2106 Datasheet Description The 8P34S2106 is a high-performance, low-power, differential dual 1:6 LVDS output 1.8V fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Two independent buffer channels are available, each channel has six low skew outputs. High isolation between channels minimizes noise coupling. AC characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S2106 ideal for those clock distribution applications demanding well-defined performance and repeatability. The device is characterized to operate from a 1.8V power supply. The integrated bias voltage references enable easy interfacing of AC-coupled signals to the device inputs. Block Diagram VDDA 51k CLKA nCLKA 51k 51k VREFA Voltage Reference A VDDA 51k SELAA VDDB 51k CLKB nCLKB 8P34S21501k4 tra51nksistor count: VREFB Voltage Reference B VDDB 51k SELAB 8P34S2106 transistor count: 1113 QA0 nQA0 QA1 nQA1 QA2 nQA2 QA3 nQA3 QA4 nQA4 QA5 nQA5 QB0 nQB0 QB1 nQB1 QB2 nQB2 QB3 nQB3 QB4 nQB4 QB5 nQB5 Features ▪ Dual 1:6 low skew, low additive jitter LVDS fanout buffers ▪ Matched AC characteristics across both channels ▪ High isolation between channels ▪ Low power consumption ▪ Both differential CLKA, nCLKA and CLKB, nCLKB inputs accept LVDS, LVPECL and single-ended LVCMOS levels ▪ Maximum input clock frequency: 2GHz ▪ Output amplitudes: 350mV, 500mV (selectable) ▪ Output bank skew: 10ps typical ▪ Output skew: 20ps typical ▪ Low additive phase jitter, RMS: 45fs typical (fREF = 156.25MHz, 12kHz - 20MHz) ▪ Full 1.8V supply voltage mode ▪ Device current consumption (IDD): 210mA typical ▪ Lead-free (RoHS 6), 40-lead VFQFN packaging ▪ -40°C to 85°C ambient operating temperature ▪ Supports case temperature up to 105°C ©2016 Integrated Device Technology, Inc. 1 October 20, 2016 1 page 8P34S2106 Datasheet Absolute Maximum Ratings NOTE: The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 8P34S2106 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 4. Absolute Maximum Ratings Item Supply voltage, VDD[a] Inputs, VI Outputs, IO Continuous current Surge current Input sink/source, IREF Maximum Junction Temperature, TJ,MAX Storage Temperature, TSTG ESD - Human Body Model[b] ESD - Charged Device Model[b] [a] VDD denotes VDDA, VDDB. [b] According to JEDEC JS-001-2012/JESD22-C101E. 4.6V -0.5V to 3.6V 10mA 15mA ±2mA 125°C -65°C to 150°C 2000V 1500V Rating DC Electrical Characteristics Table 5. DC Input Characteristics Symbol CIN RPULLDOWN RPULLUP Parameter Input capacitance Input pull-down resistor Input pull-up resistor Test Conditions Minimum Typical 2 51 51 Maximum Units pF k k Table 6. Power Supply DC Characteristics, VDDA = VDDB = VDDQA = VDDQB = 1.8V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDDQA, VDDQB VDDQA, VDDQB IDDA + IDDB + IDDQA + IDDQB Power supply voltage Output supply voltage Core and output supply current QA[0:5], QB[0:5] outputs terminated 100 between nQx, Qx 500mV amplitude 350mV amplitude 1.71 1.8 1.89 V 1.71 1.8 1.89 V 300 390 mA 210 275 mA ©2016 Integrated Device Technology, Inc. 5 October 20, 2016 5 Page 8P34S2106 Datasheet Wiring the Differential Input to Accept Single-Ended Levels Figure 3 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 1.8V and VDD = 1.8V, R1 and R2 value should be adjusted to set V1 at 0.9V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster than 1V/ns. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 3. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2016 Integrated Device Technology, Inc. 11 October 20, 2016 11 Page

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