8P73S674 PDF даташит
Спецификация 8P73S674 изготовлена «IDT» и имеет функцию, называемую «1.8V LVPECL Clock Divider». |
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Детали детали
Номер произв | 8P73S674 |
Описание | 1.8V LVPECL Clock Divider |
Производители | IDT |
логотип |
15 Pages
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1.8V LVPECL Clock Divider
8P73S674
DATA SHEET
General Description
The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer.
The device has been designed for clock signal division and fanout in
wireless base station (radio and base band), high-end computing and
telecommunication equipment. The device is optimized to deliver
excellent phase noise performance. The 8P73S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew 1.8V LVPECL outputs are available for and support clock
output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL
outputs are terminated 50 to GND. Outputs can be disabled to save
power consumption if not used. The device is packaged in a lead-free
(RoHS 6) 20-lead VFQFN package. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
• Clock signal division and distribution
• SiGe technology for high-frequency and fast signal rise/fall times
• Four low-skew LVPECL clock outputs
• Supports frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum Output frequency: 1GHz
• Output skew: 100ps (maximum)
• LVPECL output rise/fall time (20% - 80%): 220ps (maximum)
• 1.8V core and output supply mode
• Supports 1.8V I/O LVCMOS logic levels for all control pins
• -40°C to +85°C ambient operating temperature
• Lead-free (RoHS 6) 20-lead VFQFN packaging
Block Diagram
IN
nIN
VT
N[1:0]
nOEA
nOEB
2x 50
÷N
8P73S674 REVISION 1 12/17/14
Pin Assignment
Q0
nQ0
20 19 18 17 16
nIN 1
Q1
nQ1 NC 2
15 nQ1
14 Q1
Q2
VT 3
8P73S674
13 nQ2
nQ2
IN 4
12 Q2
Q3
nQ3
N0 5
11 VCC
6 7 8 9 10
20-pin, 2.15mm x 2.15mm, EPad, VFQFN Package
1 ©2014 Integrated Device Technology, Inc.
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8P73S674 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
Name
nIN
NC
VT
IN
N0
GND
N1
8 nOEB
9 nQ3
10 Q3
11 VCC
12 Q2
13 nQ2
14 Q1
15 nQ1
16 VCC
17 Q0
18 nQ0
19 nOEA
20 GND
EPAD
GND_EP
Type
Input
—
Unused
—
——
Input
—
Input
Pulldown
Power
—
Input
Pulldown
Input
Pulldown
Output
Output
Power
Output
Output
Output
Output
Power
Output
Output
—
—
—
—
—
—
—
—
—
—
Input
Pulldown
Power
—
Power
—
Description
Clock signal inverting differential input. Internal termination 50 to VT.
Not connected.
Leave open if IN, nIN is used with LVDS signals.
Clock signal non-inverting differential input. Internal termination 50 to VT.
Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.
Power supply ground.
Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.
Output enable control for the Q1, Q2 and Q3 outputs.
1.8V LVCMOS/LVTTL interface levels.
Differential clock output 3. 1.8V LVPECL output levels.
Supply voltage for the clock outputs.
Differential clock output 2. 1.8V LVPECL output levels.
Differential clock output 1. 1.8V LVPECL output levels.
Supply voltage for the clock outputs.
Differential clock output 0. 1.8V LVPECL output levels.
Output enable control for the Q0 output.
1.8V LVCMOS/LVTTL interface levels.
Power supply ground.
Exposed package pad negative supply voltage (GND).
Return current path for the Q0, Q1, Q2 and Q3 outputs.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
1.8V LVPECL CLOCK DIVIDER
2
REVISION 1 12/17/14
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Truth Tables
Table 3A. N Clock Divider
N1
0 (default)
0
1
1
Input
N0
0 (default)
1
0
1
Divider Value
÷1
÷2
÷4
÷8
Table 3B. nOEA Output Enable
Input
nOEA
0 (default)
1
Output
Q0
Output is enabled
Output is disabled in logic low state
Table 3C. nOEB Output Enable
Input
nOEB
0 (default)
1
Output
Q1, Q2, Q3
Outputs are enabled
Outputs are disabled in logic low state
8P73S674 DATA SHEET
REVISION 1 12/17/14
3 1.8V LVPECL CLOCK DIVIDER
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8P73S674 | 1.8V LVPECL Clock Divider | IDT |
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