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8SLVP1204 PDF даташит

Спецификация 8SLVP1204 изготовлена ​​​​«IDT» и имеет функцию, называемую «LVPECL Output Fanout Buffer».

Детали детали

Номер произв 8SLVP1204
Описание LVPECL Output Fanout Buffer
Производители IDT
логотип IDT логотип 

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8SLVP1204 Даташит, Описание, Даташиты
Low Phase Noise, 2:4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1204
DATA SHEET
General Description
The 8SLVP1204 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1204 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1204 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Four low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See Section, “Applications Information”, section, “Wiring
the Differential Input to Accept Single-Ended Levels” (Figures 1A
and 1B)
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input, (input select)
Output skew: 5ps (typical), at 3.63V
Propagation delay: 200ps (typical), at 3.63V
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
Maximum device current consumption (IEE): 60mA (maximum),
at 3.63V
Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
Lead-free (RoHS 6), 16-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Block Diagram
VCC
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
VCC
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0 fREF
1
SEL Pulldown
VREF
Voltage
Reference
Pin Assignment
16 15 14 13
Q0
VEE 1
12 nQ1
nQ0
SEL 2
11 Q1
Q1
PCLK1 3
10 nQ0
nQ1 nPCLK1 4
9 Q0
5 6 78
Q2
nQ2
Q3
nQ3 8SLVP1204
16-Lead, 3mm x 3mm VFQFN Package
8SLVP1204 REVISION D 6/8/15
1 ©2015 Integrated Device Technology, Inc.









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8SLVP1204 Даташит, Описание, Даташиты
8SLVP1204 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1 VEE Power
Negative supply pin.
2
SEL
Input
Pulldown Reference select control pin. See Table 3 for function. LVCMOS/LVTTL interface
levels.
3
PCLK1
Input
Pulldown Non-inverting differential LVPECL clock/data input.
4
nPCLK1
Input
Pullup/
Pulldown Inverting differential LVPECL clock/data input. VCC/2 default when left floating.
5 VCC Power
Power supply pins.
6
PCLK0
Input
Pulldown Non-inverting differential LVPECL clock/data input.
7
nPCLK0
Input
Pullup/
Pulldown Inverting differential LVPECL clock/data input. VCC/2 default when left floating.
8
9, 10
VREF
Q0, nQ0
Output
Output
Bias voltage reference for the PCLK inputs.
Differential output pair 0. LVPECL interface levels.
11, 12
Q1, nQ1
Output
Differential output pair 1. LVPECL interface levels.
13, 14
Q2, nQ2
Output
Differential output pair 2. LVPECL interface levels.
15, 16
Q3, nQ3
Output
Differential output pair 3. LVPECL interface levels.
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Selection Function Table
Input
SEL Operation
0 (default) PCLK0, nPCLK0 is the selected differential clock input.
1 PCLK1, nPCLK1 is the selected differential clock input.
NOTE: SEL is an asynchronous control.
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
2
REVISION D 6/8/15









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8SLVP1204 Даташит, Описание, Даташиты
8SLVP1204 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VCC
Inputs, VI
Outputs, IO (LVPECL)
Continuous Current
Surge Current
Input Sink/Source, IREF
Maximum Junction Temperature, TJ,MAX
Storage Temperature, TSTG
ESD - Human Body Model, NOTE 1
ESD - Charged Device Model, NOTE 1
Rating
4.6V
-0.5V to VCC + 0.5V
50mA
100mA
±2mA
125°C
-65°C to 150°C
2000V
1500V
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ±10%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VCC Power Supply Voltage
IEE Power Supply Current
ICC Power Supply Current
Q0 to Q3 terminated 50to VCC – 2V
2.97
3.3V
53
170
Maximum
3.63
60
204
Units
V
mA
mA
Table 4B. Power Supply DC Characteristics, VCC = 3.3V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VCC Power Supply Voltage
IEE Power Supply Current
ICC Power Supply Current
Q0 to Q3 terminated 50to VCC – 2V
3.135
3.3V
53
170
Maximum
3.465
60
204
Units
V
mA
mA
Table 4C. Power Supply DC Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VCC Power Supply Voltage
IEE Power Supply Current
ICC Power Supply Current
Q0 to Q3 terminated 50to VCC – 2V
2.375
2.5V
49
170
Maximum
2.625
55
199
Units
V
mA
mA
REVISION D 6/8/15
3 LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER










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