CD3207BB PDF даташит
Спецификация CD3207BB изготовлена «NXP Semiconductors» и имеет функцию, называемую «7-bit Futurebus transceiver». |
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Детали детали
Номер произв | CD3207BB |
Описание | 7-bit Futurebus transceiver |
Производители | NXP Semiconductors |
логотип |
14 Pages
No Preview Available ! |
INTEGRATED CIRCUITS
FB2041
7-bit Futurebus+ transceiver
Product specification
IC19 Data Handbook
1995 May 25
Philips
Semiconductors
No Preview Available ! |
Philips Semiconductors
7-bit Futurebus+ transceiver
Product specification
FB2041
DESCRIPTION
The FB2041 is a 7-bit bidirectional BTL transceiver and is intended
to provide the electrical interface to a high performance wired-OR
bus. The FB2041 is an inverting transceiver.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
FEATURES
• 7-bit BTL transceiver
• Separate I/O on TTL A-port
• Inverting
• Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement
• Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
• High drive 100mA BTL open collector drivers on B-port
• Allows incident wave switching in heavily loaded backplane buses
• Reduced BTL voltage swing produces less noise and reduces
power consumption
• Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Controlled output ramp and multiple GND pins minimize ground
bounce
• Each BTL driver has a dedicated Bus GND for a signal return
• Glitch-free power up/power down operation
• Low ICC current
• Tight output skew
• Supports live insertion
• Pins for the optional JTAG boundary scan function are provided
• High density packaging in plastic Quad Flatpack
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH Propagation delay
tPHL
AIn to Bn
tPLH Propagation delay
tPHL
Bn to AOn
COB Output capacitance (B0 - B6 only)
IOL Output current (B0 - B6 only)
Standby
ICC Supply Current
AIn to Bn (outputs Low or High)
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
TYPICAL
3.7
2.7
3.4
3.2
6
100
19
40
22
19
UNIT
ns
ns
pF
mA
mA
ORDERING INFORMATION
PACKAGE
52-pin Plastic Quad Flatpack
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0 to +70°C
FB2041BB
INDUSTRIAL RANGE
VCC = 5V±10%; Tamb = -40 to +85°C
CD3207BB
DWG
No.
SOT379-1
1995 May 25
2 853-1561 15279
No Preview Available ! |
Philips Semiconductors
7-bit Futurebus+ transceiver
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND 1
AI1 2
AI2 3
AO2 4
LOGIC GND
AO3
LOGIC GND
5
6
7
AI3 8
AI4 9
AO4 10
LOGIC GND 11
AO5 12
LOGIC GND 13
7-Bit Transceiver
FB2041
52-lead PQFP
39 BUS GND
38 B1
37 BUS GND
36 B2
35 BUS GND
34 B3
33 BUS GND
32 B4
31 BUS GND
30 B5
29 BUS GND
28 B6
27 BUS GND
14 15 16 17 18 19 20 21 22 23 24 25 26
Product specification
FB2041
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1, output drivers for bits 1–2–3 are enabled with
OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with
OEA3/OEB3.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when VCC is below 2.5V.
The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn is Low the output driver will
be enabled. When OEB0 is Low or if OEBn is High, the B-port
drivers will be inactive and at the level of the backplane signal.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
5V level while VCC is Low. If live insertion is not a requirement, the
BIAS V pin should be tied to a VCC pin.
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
The LOGIC VCC and BUS VCC pins are also isolated internally to
minimize noise and may be externally decoupled separately or
simply tied together.
JTAG boundary scan functionality is provided as an option with
signals TMS, TCK, TDI and TDO. When this option is not present,
TMS and TCK are no-connects (no bond wires) and TDI and TDO
are shorted together internally.
1995 May 25
3
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CD3207BB | 7-bit Futurebus transceiver | NXP Semiconductors |
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