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9FGL06 PDF даташит

Спецификация 9FGL06 изготовлена ​​​​«IDT» и имеет функцию, называемую «6-output 3.3V PCIe Clock Generator».

Детали детали

Номер произв 9FGL06
Описание 6-output 3.3V PCIe Clock Generator
Производители IDT
логотип IDT логотип 

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9FGL06 Даташит, Описание, Даташиты
6-output 3.3V PCIe Clock Generator
9FGL06
DATASHEET
Description
The 9FGL06 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 6 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL06
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL06P1 can be programmed with a
user-defined power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
6 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
9FGL0641 default ZOUT = 100
9FGL0651 default ZOUT = 85
9FGL06P1 factory programmable defaults
1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC-compliant
PCIe Gen2-3 SRIS-compliant
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF 12k-20M phase jitter is <2ps rms when SSC is off
REF phase jitter is <300fs rms, SSC off, and <1.5ps rms,
SSC is On
±100ppm frequency accuracy on all clocks
Block Diagram
Features/Benefits
Direct connection to 100(xx41) or 85(xx51)
transmission lines; saves 24 resistors compared to
standard PCIe devices
172mW typical power consumption (@3.3V); eliminates
thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
differential output amplitude
33, 85 or 100output impedance for each output
spread spectrum amount
41 and 51 devices contain default configuration; SMBus
interface not required for device operation
P1 device allows factory programming of customer-defined
SMBus power up default; allows exact optimization to
customer requirements
8MHz - 40MHz input frequency with 9FGL08P1 device
(25MHz default); flexibility
OE# pins; support DIF power management
Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
DIF outputs blocked until PLL is locked; clean system
start-up
Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
vOE(5:0)#
XIN/CLKIN_25
603-25-150JA4I 25MHz
X2
6
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SSC Capable
PLL
REF
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL06 OCTOBER 19, 2016
1 ©2016 Integrated Device Technology, Inc.









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9FGL06 Даташит, Описание, Даташиты
9FGL06 DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSS_EN_tri 1
30 vOE3#
X1_25 2
29 DIF3#
X2 3
28 DIF3
VDDXTAL3.3 4
VDDREF3.3 5
9FGL06xx
27 VDDIO
26 VDDA3.3
vSADR/REF3.3 6
epad is GND
25 NC
NC 7
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
SMBus Address Selection Table
40-pin VFQFPN, 5x5 mm, 0.4mm pitch
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table3
CKPWRGD_PD#
0
1
1
1
SMBus
OE bit
X
1
1
0
OEx# Pin
X
0
1
X
DIFx
True O/P Comp. O/P
REF
Low1
Low1
Hi-Z2
Running
Running Running
Disabled1 Disabled1 Running
Disabled1 Disabled1 Disabled4
1. The output state is set by B11[1:0] (Low/Low default)
2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is disabled unless Byte3[5]=1, in which case REF is
running.
3. Input polarities defined at default values for 9FGL0641/0651.
4. See SMBus description for Byte 3, bit 4
Power Connections
Pin Number
VDD
4
5
11
VDDIO
GND
41
41
8
12,17,27,32,39 41
26 41
Description
XTAL OSC
REF Power
Digital (dirty)
Power
DIF outputs
PLL Analog
6-OUTPUT 3.3V PCIE CLOCK GENERATOR
2
OCTOBER 19, 2016









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9FGL06 Даташит, Описание, Даташиты
9FGL06 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 vSS_EN_tri
2 X1_25
3 X2
4 VDDXTAL3.3
5 VDDREF3.3
6 vSADR/REF3.3
7 NC
8 GNDDIG
9 SCLK_3.3
10 SDATA_3.3
11 VDDDIG3.3
12 VDDIO
13 vOE0#
14 DIF0
15 DIF0#
16 VDD3.3
17 VDDIO
18 DIF1
19 DIF1#
20 NC
21 vOE1#
22 DIF2
23 DIF2#
24 vOE2#
25 NC
26 VDDA3.3
27 VDDIO
28 DIF3
29 DIF3#
30 vOE3#
31 VDD3.3
32 VDDIO
33 DIF4
34 DIF4#
35 vOE4#
36 DIF5
37 DIF5#
38 vOE5#
39 VDDIO
40 ^CKPWRGD_PD#
41 ePAD
PIN TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
IN 1 = -0.5% spread, M = -0.25%, 0 = Spread Off
IN Crystal input, Nominally 25.00MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 3.3V
PWR VDD for REF output. nominal 3.3V.
LATCHED Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin
I/O
N/A No Connection.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V digital power (dirty power)
PWR Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 3.3V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
N/A No Connection.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
N/A No Connection.
PWR 3.3V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 3.3V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND Connect paddle to ground.
OCTOBER 19, 2016
3 6-OUTPUT 3.3V PCIE CLOCK GENERATOR










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