DataSheet26.com

9FGL08 PDF даташит

Спецификация 9FGL08 изготовлена ​​​​«IDT» и имеет функцию, называемую «8-output 3.3V PCIe Clock Generator».

Детали детали

Номер произв 9FGL08
Описание 8-output 3.3V PCIe Clock Generator
Производители IDT
логотип IDT логотип 

19 Pages
scroll

No Preview Available !

9FGL08 Даташит, Описание, Даташиты
8-output 3.3V PCIe Clock Generator
9FGL08
Description
The 9FGL08 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 8 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL08
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL08P1 can be programmed with a
user-defined power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
8 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
9FGL0841 default ZOUT = 100
9FGL0851 default ZOUT = 85
9FGL08P1 factory programmable defaults
1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC-compliant
PCIe Gen2-3 SRIS-compliant
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF 12k-20M phase jitter is <2ps rms when SSC is off
REF phase jitter is <300fs rms, SSC off, and <1.5ps rms,
SSC is On
±100ppm frequency accuracy on all clocks
Block Diagram
DATASHEET
Features/Benefits
Direct connection to 100(xx41) or 85(xx51)
transmission lines; saves 32 resistors compared to
standard PCIe devices
206mW typical power consumption (62mA*3.3V);
eliminates thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
differential output amplitude
33, 85 or 100output impedance for each output
spread spectrum amount
41 and 51 devices contain default configuration; SMBus
interface not required for device operation
P1 device allows factory programming of customer-defined
input/output frequencies and SMBus power up default;
allows exact optimization to customer requirements.
8MHz - 40MHz input frequency with 9FGL08P1 device
(25MHz default); flexibility
OE# pins; support DIF power management
Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
DIF outputs blocked until PLL is locked; clean system
start-up
Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
603-25-150JA4I 25MHz
X2
8
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SSC Capable
PLL
REF
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL08 OCTOBER 19, 2016
1 ©2016 Integrated Device Technology, Inc.









No Preview Available !

9FGL08 Даташит, Описание, Даташиты
9FGL08 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri 1
36 DIF5#
GNDXTAL 2
35 DIF5
XIN/CLKIN_25 3
34 vOE4#
X2 4
33 DIF4#
VDDXTAL3.3 5
VDDREF3.3 6
9FGL0841/51/P1
32 DIF4
31 VDDIO
vSADR/REF3.3 7
GNDREF 8
epad is GND
30 VDDA3.3
29 GNDA
GNDDIG 9
28 vOE3#
SCLK_3.3 10
27 DIF3#
SDATA_3.3 11
26 DIF3
VDDDIG3.3 12
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
SMBus Address Selection Table
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
vv prefix indicates internal 60KOhm pull down resistor
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table3
CKPWRGD_PD#
SMBus
OE bit
OEx# Pin
DIFx/DIFx#
True O/P Comp. O/P
REF
0
X
X
Low1
Low1
Hi-Z2
1
1
0
Running
Running Running
1 1 1 Disabled1 Disabled1 Running
1 0 X Disabled1 Disabled1 Disabled4
1. The output state is set by B11[1:0] (Low/Low default)
2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is disabled unless Byte3[5]=1, in which case REF is
running..
3. Input polarities defined at default values for 9FGL0841/0851.
4. See SMBus description for Byte 3, bit 4
Power Connections
Pin Number
VDD
5
6
12
20,38
30
VDDIO
13,21,31,39,
47
GND
2
8
9
22,29,40,
49
29
Description
XTAL OSC
REF Power
Digital (dirty)
Power
DIF outputs
PLL Analog
8-OUTPUT 3.3V PCIE CLOCK GENERATOR
2
OCTOBER 19, 2016









No Preview Available !

9FGL08 Даташит, Описание, Даташиты
9FGL08 DATASHEET
Pin Descriptions
PIN # PIN NAME
1 vSS_EN_tri
2 GNDXTAL
3 XIN/CLKIN_25
4 X2
5 VDDXTAL3.3
6 VDDREF3.3
7 vSADR/REF3.3
8 GNDREF
9 GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG3.3
13 VDDIO
14 vOE0#
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
20 VDD3.3
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
26 DIF3
27 DIF3#
28 vOE3#
29 GNDA
30 VDDA3.3
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
37 vOE5#
38 VDD3.3
39 VDDIO
TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
IN 1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND GND for XTAL
IN Crystal input or Reference Clock input. Nominally 25MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 3.3V
PWR VDD for REF output. nominal 3.3V.
LATCHED Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin
I/O
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V digital power (dirty power)
PWR Power supply for differential outputs
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 3.3V
PWR Power supply for differential outputs
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin for the PLL core.
PWR 3.3V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 3.3V
PWR Power supply for differential outputs
OCTOBER 19, 2016
3 8-OUTPUT 3.3V PCIE CLOCK GENERATOR










Скачать PDF:

[ 9FGL08.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
9FGL022-output 3.3V PCIe Clock GeneratorIDT
IDT
9FGL044-output 3.3V PCIe Clock GeneratorIDT
IDT
9FGL066-output 3.3V PCIe Clock GeneratorIDT
IDT
9FGL088-output 3.3V PCIe Clock GeneratorIDT
IDT

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск