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9FGU0241 PDF даташит

Спецификация 9FGU0241 изготовлена ​​​​«IDT» и имеет функцию, называемую «2 O/P 1.5V PCIe Gen1-2-3 Clock Generator».

Детали детали

Номер произв 9FGU0241
Описание 2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
Производители IDT
логотип IDT логотип 

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9FGU0241 Даташит, Описание, Даташиты
2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0241
DATASHEET
Description
The 9FGU0241 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 2 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
2 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo=100
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
23mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 24-pin 4x4 mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
X2
vOE(1:0)#
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF1
DIF0
9FGU0241 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.









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9FGU0241 Даташит, Описание, Даташиты
9FGU0241 DATASHEET
Pin Configuration
XIN/CLKIN_25 1
X2 2
VDDXTAL1.5 3
vSADR/REF1.5 4
GNDREF 5
GNDDIG 6
24 23 22 21 20 19
18 DIF1#
17 DIF1
9FGU0241
16 VDDA1.5
15 GNDA
14 DIF0#
13 DIF0
7 8 9 10 11 12
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
SMBus
OE bit
X
1
0
DIFx
True O/P Comp. O/P
Low Low
Running
Running
Low Low
REF
Hi-Z1
Running
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this,
when CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
VDD
3
7
11,20
16
GND
5,24
6
10,21
15
Description
XTAL, REF
Digital Power
DIF outputs
PLL Analog
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
2
OCTOBER 18, 2016









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9FGU0241 Даташит, Описание, Даташиты
9FGU0241 DATASHEET
Pin Descriptions
Pin#
1
2
3
Pin Name
XIN/CLKIN_25
X2
VDDXTAL1.5
4 vSADR/REF1.5
5 GNDREF
6 GNDDIG
7 VDDDIG1.5
8 SCLK_3.3
9 SDATA_3.3
10 GND
11 VDD1.5
12 vOE0#
13 DIF0
14 DIF0#
15 GNDA
16 VDDA1.5
17 DIF1
18 DIF1#
19 vOE1#
20 VDD1.5
21 GND
22 ^CKPWRGD_PD#
23 vSS_EN_tri
24 GNDXTAL
Type Pin Description
IN Crystal input or Reference Clock input. Nominally 25MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 1.5V
LATCHED
I/O
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
PWR 1.5V digital power (dirty power)
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
GND Ground pin.
PWR Power supply, nominally 1.5V
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin for the PLL core.
PWR 1.5V power for the PLL core.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominally 1.5V
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
LATCHED IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND GND for XTAL
OCTOBER 18, 2016
3 2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS










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