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9FGU0441 PDF даташит

Спецификация 9FGU0441 изготовлена ​​​​«IDT» и имеет функцию, называемую «4 O/P 1.5V PCIe Gen1-2-3 Clock Generator».

Детали детали

Номер произв 9FGU0441
Описание 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
Производители IDT
логотип IDT логотип 

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9FGU0441 Даташит, Описание, Даташиты
4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0441
DATASHEET
Description
The 9FGU0441 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 4 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
4 - 100MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100ohms
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Block Diagram
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
39mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
XIN/CLKIN_25
X2
vOE(3:0)#
OSC
REF1.5
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
DIF3
DIF2
DIF1
DIF0
9FGU0441 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.









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9FGU0441 Даташит, Описание, Даташиты
9FGU0441 DATASHEET
Pin Configuration
GNDXTAL 1
XIN/CLKIN_25 2
X2 3
VDDXTAL1.5 4
VDDREF1.5 5
vSADR/REF1.5 6
GNDREF 7
GNDDIG 8
32 31 30 29 28 27 26 25
9FGU0441
9 10 11 12 13 14 15 16
24 vOE2#
23 DIF2#
22 DIF2
21 VDDA1.5
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table
CKPWRGD_PD#
SMBus
DIFx
OE bit OEx# True O/P Comp. O/P
REF
0
X X Low
Low Hi-Z1
1
1
0 Running
Running Running
1
0 1 Low
Low Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
VDD
4
5
9
16, 25
21
GND
1
7
8, 30
15, 26
20
Description
XTAL Analog
REF Output
Digital Power
DIF outputs
PLL Analog
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
2
OCTOBER 18, 2016









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9FGU0441 Даташит, Описание, Даташиты
9FGU0441 DATASHEET
Pin Descriptions
Pin#
1
2
3
4
5
Pin Name
GNDXTAL
XIN/CLKIN_25
X2
VDDXTAL1.5
VDDREF1.5
6 vSADR/REF1.5
7 GNDREF
8 GNDDIG
9 VDDDIG1.5
10 SCLK_3.3
11 SDATA_3.3
12 vOE0#
13 DIF0
14 DIF0#
15 GND
16 VDDO1.5
17 vOE1#
18 DIF1
19 DIF1#
20 GNDA
21 VDDA1.5
22 DIF2
23 DIF2#
24 vOE2#
25 VDDO1.5
26 GND
27 DIF3
28 DIF3#
29 vOE3#
30 GND
31 ^CKPWRGD_PD#
32 vSS_EN_tri
Type Pin Description
GND GND for XTAL
IN Crystal input or Reference Clock input. Nominally 25MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 1.5V
PWR VDD for REF output. nominal 1.5V.
LATCHED
I/O
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
PWR 1.5V digital power (dirty power)
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin.
PWR Power supply for outputs, nominally 1.5V.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin for the PLL core.
PWR 1.5V power for the PLL core.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for outputs, nominally 1.5V.
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
LATCHED IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
OCTOBER 18, 2016
3 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS










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