9FGV0231 PDF даташит
Спецификация 9FGV0231 изготовлена «IDT» и имеет функцию, называемую «2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR». |
|
Детали детали
Номер произв | 9FGV0231 |
Описание | 2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR |
Производители | IDT |
логотип |
15 Pages
No Preview Available ! |
2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
DATASHEET
9FGV0231
Description
The 9FGV0231 is a 2-output very low power clock
generator for PCIe Gen 1, 2 and 3 applications. The device
has 2 output enables for clock management and supports 2
different spread spectrum levels in addition to spread off.
Recommended Application
PCIe Gen1-2-3 clock generator
Output Features
• 2 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs
• 1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• REF phase jitter is <1.5ps RMS
Features/Benefits
• 1.8V operation; reduced power consumption
• OE# pins; support DIF power management
• LP-HCSL differential clock outputs; reduced power and
board space
• Programmable Slew rate for each output; allows tuning
for various line lengths
• Programmable output amplitude; allows tuning for
various application environments
• DIF outputs blocked until PLL is locked; clean system
start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy
controllers
• Space saving 24-pin 4x4 mm VFQFPN; minimal board
space
Block Diagram
X1_25
X2
OE(1:0)#
OSC
SS Capable PLL
SADR
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
REF1.8
2
DIF(1:0)
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
1
9FGV0231 OCTOBER 18, 2016
No Preview Available ! |
9FGV0231
2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
Pin Configuration
X1_25 1
X2 2
VDDXTAL1.8 3
vSADR/REF1.8 4
GNDREF 5
GNDDIG 6
24 23 22 21 20 19
18 DIF1#
17 DIF1
9FGV0231
16 VDDA1.8
15 GNDA
14 DIF0#
13 DIF0
7 8 9 10 11 12
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
SMBus
OE bit
X
1
0
DIFx
True O/P Comp. O/P
Low Low
Running
Running
Low Low
REF
Hi-Z1
Running
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this,
when CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
VDD
3
7
11,20
16
GND
5,24
6
10,21
15
Description
XTAL, REF
Digital
DIF outputs
PLL Analog
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
2
9FGV0231 OCTOBER 18, 2016
No Preview Available ! |
9FGV0231
2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
Pin Descriptions
Pin#
1
2
3
Pin Name
X1_25
X2
VDDXTAL1.8
4 vSADR/REF1.8
5 GNDREF
6 GNDDIG
7 VDDDIG1.8
8 SCLK_3.3
9 SDATA_3.3
10 GND
11 VDD1.8
12 vOE0#
13 DIF0
14 DIF0#
15 GNDA
16 VDDA1.8
17 DIF1
18 DIF1#
19 vOE1#
20 VDD1.8
21 GND
22 ^CKPWRGD_PD#
23 vSS_EN_tri
24 GNDXTAL
Type Pin Description
IN Crystal input, Nominally 25.00MHz.
OUT
Crystal output.
PWR Power supply for XTAL, nominal 1.8V
LATCHED
I/O
Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin.
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
PWR 1.8V digital power (dirty power)
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
GND Ground pin.
PWR Power supply, nominal 1.8V
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND Ground pin for the PLL core.
PWR 1.8V power for the PLL core.
OUT
Differential true clock output
OUT
Differential Complementary clock output
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 1.8V
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
LATCHED IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND GND for XTAL
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
3
9FGV0231 OCTOBER 18, 2016
Скачать PDF:
[ 9FGV0231.PDF Даташит ]
Номер в каталоге | Описание | Производители |
9FGV0231 | 2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR | IDT |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |