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9DB1233 PDF даташит

Спецификация 9DB1233 изготовлена ​​​​«IDT» и имеет функцию, называемую «Twelve Output Differential Buffer».

Детали детали

Номер произв 9DB1233
Описание Twelve Output Differential Buffer
Производители IDT
логотип IDT логотип 

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9DB1233 Даташит, Описание, Даташиты
Twelve Output Differential Buffer for PCIe Gen3
DATASHEET
9DB1233
Recommended Application
12 output PCIe Gen3 zero-delay/fanout buffer
General Description
The 9DB1233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe Gen2
and Gen1. The 9DB1233 is driven by a differential SRC output
pair from an IDT 932S421 or 932SQ420 or equivalent main
clock generator. It attenuates jitter on the input clock and has a
selectable PLL bandwidth to maximize performance in systems
with or without Spread-Spectrum clocking.
Output Features
• 12 - 0.7V current mode differential HCSL output pairs
Features/Benefits
• 3 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 12 OE# pins/Hardware control of each output
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Supports undriven differential outputs in Power Down mode
for power management
Key Specifications
• Output cycle-cycle jitter < 50ps.
• Output-to-output skew < 50 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
• Pin compatible with DB1200 Yellow Cover Device
Functional Block Diagram
12
OE_(11:0)#
DIF_IN
DIF_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
12
DIF(11:0))
HIGH_BW#
BYPASS#/PLL
VTTPWRGD#/PD
ADR_SEL
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT® Twelve Output Differential Buffer for PCIe Gen3
1
1675B—11/08/10









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9DB1233 Даташит, Описание, Даташиты
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Pin Configuration
VDD 1
64 VDDA
DIF_IN 2
63 AGND
DIF_IN# 3
62 IREF
GND 4
61 VDD
OE0# 5
60 OE11#
DIF_0 6
59 DIF_11
DIF_0# 7
58 DIF_11#
VDD 8
57 VDD
GND 9
56 GND
OE1# 10
55 OE10#
DIF_1 11
54 DIF_10
DIF_1# 12
53 DIF_10#
OE2# 13
52 OE9#
DIF_2 14
51 DIF_9
DIF_2# 15
50 DIF_9#
GND 16
49 GND
VDD 17
48 VDD
OE3# 18
47 OE8#
DIF_3 19
46 DIF_8
DIF_3# 20
45 DIF_8#
OE4# 21
44 OE7#
DIF_4 22
43 DIF_7
DIF_4# 23
42 DIF_7#
VDD 24
41 VDD
GND 25
40 GND
OE5# 26
39 OE6#
DIF_5 27
38 DIF_6
DIF_5# 28
37 DIF_6#
**ADR_SEL 29
36 VTTPWRGD#/PD
HIGH_BW# 30
35 BYPASS#/PLL
VDD 31
34 GND
SMBCLK 32
33 SMBDAT
64-TSSOP
** Indicates 120K ohm Pulldown
SMBus Address Selection (Pin 29)
ADR_SEL
Voltage SMBus Adr (Wr/Rd)
Low <0.8V
DC/DD
Mid 1.2<Vin<1.8V
D6/D7
High
Vin > 2.0V
D4/D5
Power Groups
Pin Number
VDD
GND
Description
1 4 DIF_IN/DIF_IN#
8, 17, 24, 41, 9, 16, 25, 40,
48, 57
49, 56
N/A 63
DIF(11:0)
IREF
64 63 Analog VDD & GND
for PLL core
Note: Please treat pin 1 as an analog VDD.
IDT® Twelve Output Differential Buffer for PCIe Gen3
2
1675B—11/08/10









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9DB1233 Даташит, Описание, Даташиты
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Pin Description
PIN #
PIN NAME
1 VDD
2 DIF_IN
3 DIF_IN#
4 GND
5 OE0#
6 DIF_0
7 DIF_0#
8 VDD
9 GND
10 OE1#
11 DIF_1
12 DIF_1#
13 OE2#
14 DIF_2
15 DIF_2#
16 GND
17 VDD
18 OE3#
19 DIF_3
20 DIF_3#
21 OE4#
22 DIF_4
23 DIF_4#
24 VDD
25 GND
26 OE5#
27 DIF_5
28 DIF_5#
29 **ADR_SEL
30 HIGH_BW#
31 VDD
32 SMBCLK
TYPE
PWR
IN
IN
PWR
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
IN
PWR
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
Ground pin.
Active low input for enabling DIF pair 0.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
This tri-level input selects one of 3 SMBus addresses. See the SMBus
Address Select Table for the addresses.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
Clock pin of SMBUS circuitry, 5V tolerant
IDT® Twelve Output Differential Buffer for PCIe Gen3
3
1675B—11/08/10










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Номер в каталогеОписаниеПроизводители
9DB1233Twelve Output Differential BufferIDT
IDT

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