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9DB1904B PDF даташит

Спецификация 9DB1904B изготовлена ​​​​«IDT» и имеет функцию, называемую «19 Output Differential Buffer».

Детали детали

Номер произв 9DB1904B
Описание 19 Output Differential Buffer
Производители IDT
логотип IDT логотип 

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9DB1904B Даташит, Описание, Даташиты
Datasheet
19 Output Differential Buffer for PCIe Gen2 and QPI
9DB1904B
Description
The 9DB1904 is electrically compatible to the Intel DB1900GS
Differential Buffer Specification.This buffer provides 19 output clocks
for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential
clock from a CK410B+ main clock generator, such as the
ICS932S421 drives the 9DB1904. The 9DB1904 can provide
outputs up to 400MHz in Bypass Mode.
Recommended Application
19 Output Differential Buffer for PCIe Gen2 and QPI
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 150ps across all outputs
Features/Benefits
• Power up default is all outputs in 1:1 mode/No SMBus
programming
• Spread spectrum compatible/EMI reductions
• Supports output frequencies up to 400 MHz in bypass
mode/flexible fanout buffer
• 8 Selectable SMBus addresses/no SMBus
segmentation required
• SMBus address determines PLL or Bypass mode/pin
savings
• Dedicated VDDA and CKPWRGD_PD# pins/easy board
design
Functionality at Power Up (PLL Mode)
100M_133M#
CLK_IN
MHz
1 100MHz
0 133MHz
Pin Configuration
DIF_(18:0)
MHz
CLK_IN
CLK_IN
Power Down Functionality
INPUTS
CKPWRGD_ CLK_IN/
PD#
CLK_IN#
1 Running
0X
OUTPUTS
DIF/DIF#
Running
Hi-Z
PLL State
ON
OFF
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF 1
GNDA 2
VDDA 3
HIGH_BW# 4
100M_133M#_LV 5
DIF_0 6
DIF_0# 7
DIF_1 8
DIF_1# 9
GND 10
9DB1904BKLF
VDD 11
DIF_2 12
DIF_2# 13
DIF_3 14
DIF_3# 15
DIF_4 16
DIF_4# 17
OE_01234# 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 OE14#
53 DIF_13#
52 DIF_13
51 OE13#
50 DIF_12#
49 DIF_12
48 OE12#
47 VDD
46 GND
45 DIF_11#
44 DIF_11
43 OE11#
42 DIF_10#
41 DIF_10
40 OE10#
39 DIF_9#
38 DIF_9
37 OE9#
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1
1607C —04/19/11









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9DB1904B Даташит, Описание, Даташиты
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
This pin establishes the reference for the differential current-mode output
1 IREF
OUT
pairs. It requires a fixed precision resistor to ground. 475ohm is the standard
value for 100ohm differential impedance. Other impedances require different
values. See data sheet.
2 GNDA
PWR Ground pin for the PLL core.
3 VDDA
PWR 3.3V power for the PLL core.
4 HIGH_BW#
IN 3.3V input for selecting PLL Band Width
0 = High, 1= Low
5 100M_133M#_LV
IN Low Threshold Input to select operating frequency.
See Functionality Table for Definition
6 DIF_0
OUT 0.7V differential true clock output
7 DIF_0#
OUT 0.7V differential Complementary clock output
8 DIF_1
OUT 0.7V differential true clock output
9 DIF_1#
OUT 0.7V differential Complementary clock output
10 GND
PWR Ground pin.
11 VDD
PWR Power supply, nominal 3.3V
12 DIF_2
OUT 0.7V differential true clock output
13 DIF_2#
OUT 0.7V differential Complementary clock output
14 DIF_3
OUT 0.7V differential true clock output
15 DIF_3#
OUT 0.7V differential Complementary clock output
16 DIF_4
OUT 0.7V differential true clock output
17 DIF_4#
OUT 0.7V differential Complementary clock output
18 OE_01234#
IN Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 =disable outputs, 0 = enable outputs
19 SMBCLK
IN Clock pin of SMBUS circuitry, 5V tolerant
20 SMBDAT
I/O Data pin of SMBUS circuitry, 5V tolerant
21 OE5#
IN
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
22 DIF_5
OUT 0.7V differential true clock output
23 DIF_5#
OUT 0.7V differential Complementary clock output
24 OE6#
IN Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
25 DIF_6
OUT 0.7V differential true clock output
26 DIF_6#
OUT 0.7V differential Complementary clock output
27 VDD
PWR Power supply, nominal 3.3V
28 GND
PWR Ground pin.
29 OE7#
IN Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
30 DIF_7
OUT 0.7V differential true clock output
31 DIF_7#
OUT 0.7V differential Complementary clock output
32 OE8#
IN Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
33 DIF_8
OUT 0.7V differential true clock output
34 DIF_8#
OUT 0.7V differential Complementary clock output
35 SMB_A0
IN SMBus address bit 0 (LSB)
36 SMB_A1
IN SMBus address bit 1
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
2









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9DB1904B Даташит, Описание, Даташиты
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Pin Description (continued)
PIN #
PIN NAME
37 OE9#
38 DIF_9
39 DIF_9#
40 OE10#
41 DIF_10
42 DIF_10#
43 OE11#
44 DIF_11
45 DIF_11#
46 GND
47 VDD
48 OE12#
49 DIF_12
50 DIF_12#
51 OE13#
52 DIF_13
53 DIF_13#
54 OE14#
55 DIF_14
56 DIF_14#
57 CKPWRGD_PD#
58 DIF_15
59 DIF_15#
60 OE15_16#
61 DIF_ 16
62 DIF_16#
63 VDD
64 GND
65 DIF_17
66 DIF_17#
67 DIF_18
68 DIF_18#
69 OE17_18#
70 CLK_IN
71 CLK_IN#
72 SMB_A2_PLLBYP#
PIN TYPE
DESCRIPTION
IN Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
IN
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
IN Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Ground pin.
PWR Power supply, nominal 3.3V
IN Active low input for enabling DIF pair 12.
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
IN Active low input for enabling DIF pair 13.
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
IN Active low input for enabling DIF pair 14.
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
3.3V Input notifies device to sample latched inputs and start up on first high
IN assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
IN
Active low input for enabling DIF pairs 15 and 16.
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Power supply, nominal 3.3V
PWR Ground pin.
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
IN Active low input for enabling DIF pairs 17 and 18.
1 =disable outputs, 0 = enable outputs
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
IN the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
3










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Номер в каталогеОписаниеПроизводители
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