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9DB1933 PDF даташит

Спецификация 9DB1933 изготовлена ​​​​«IDT» и имеет функцию, называемую «Nineteen Output Differential Buffer».

Детали детали

Номер произв 9DB1933
Описание Nineteen Output Differential Buffer
Производители IDT
логотип IDT логотип 

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9DB1933 Даташит, Описание, Даташиты
Nineteen Output Differential Buffer for PCIe Gen3
DATASHEET
9DB1933
Recommended Application
19 output PCIe Gen3 zero-delay/fanout buffer
General Description
The 9DB1933 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe Gen2
and Gen1. The 9DB1933 is driven by a differential SRC output
pair from an IDT 932S421, 932SQ420, or equivalent, main
clock generator. It attenuates jitter on the input clock and has a
selectable PLL bandwidth to maximize performance in systems
with or without Spread-Spectrum clocking.
Output Features
• 19 - 0.7V current mode differential HCSL output pairs
Features/Benefits
• 8 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 11 dedicated and 3 group OE# pins/Hardware control of the
outputs
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Supports undriven differential outputs in Power Down mode
for power management
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew < 150 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
Functional Block Diagram
OE(17_18)#
OE(15_16)#
OE(14:5)#,
OE_01234#
13
DIF_IN
DIF_IN#
HIGH_BW#
CKPWRGD/PD#
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
Logic
PLL
(SS Compatible)
19
DIF(18:0)
IREF
IDT® Nineteen Output Differential Buffer for PCIe Gen3
1
1676A—07/12/10









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9DB1933 Даташит, Описание, Даташиты
9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF 1
GNDA 2
VDDA 3
HIGH_BW# 4
VDD 5
DIF_0 6
DIF_0# 7
DIF_1 8
DIF_1# 9
GND 10
9DB1933AKLF
VDD 11
DIF_2 12
DIF_2# 13
DIF_3 14
DIF_3# 15
DIF_4 16
DIF_4# 17
OE_01234# 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 OE14#
53 DIF_13#
52 DIF_13
51 OE13#
50 DIF_12#
49 DIF_12
48 OE12#
47 VDD
46 GND
45 DIF_11#
44 DIF_11
43 OE11#
42 DIF_10#
41 DIF_10
40 OE10#
39 DIF_9#
38 DIF_9
37 OE9#
Power Down Functionality
INPUTS
CKPWRGD/
DIF_IN/
PD# DIF_IN#
1 Running
0X
Power Groups
Pin Number
VDD
GND
32
5,11,27,47,63 10,28,46,64
OUTPUTS
DIF/DIF#
Running
Hi-Z
Description
PLL, Analog
DIF clocks
IDT® Nineteen Output Differential Buffer for PCIe Gen3
2
PLL State
ON
OFF
1676A—07/12/10









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9DB1933 Даташит, Описание, Даташиты
9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
Pin Description
PIN #
PIN NAME
1 IREF
2 GNDA
3 VDDA
4 HIGH_BW#
5 VDD
6 DIF_0
7 DIF_0#
8 DIF_1
9 DIF_1#
10 GND
11 VDD
12 DIF_2
13 DIF_2#
14 DIF_3
15 DIF_3#
16 DIF_4
17 DIF_4#
18 OE_01234#
19 SMBCLK
20 SMBDAT
21 OE5#
22 DIF_5
23 DIF_5#
24 OE6#
25 DIF_6
26 DIF_6#
27 VDD
28 GND
29 OE7#
30 DIF_7
31 DIF_7#
32 OE8#
33 DIF_8
34 DIF_8#
35 SMB_A0
36 SMB_A1
PIN TYPE
OUT
PWR
PWR
IN
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
I/O
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
IN
DESCRIPTION
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 =disable outputs, 0 = enable outputs
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
SMBus address bit 0 (LSB)
SMBus address bit 1
IDT® Nineteen Output Differential Buffer for PCIe Gen3
3
1676A—07/12/10










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Номер в каталогеОписаниеПроизводители
9DB1933Nineteen Output Differential BufferIDT
IDT

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