PDF 9DB233 Data sheet ( Hoja de datos )

Número de pieza	9DB233
Descripción	Two Output Differential Buffer
Fabricantes	IDT
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No Preview Available ! DATASHEET Two Output Differential Buffer for PCIe Gen3 9DB233 Recommended Application: 2 output PCIe Gen3 zero-delay/fanout buffer General Description: The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB233 suitable for Express Card applications. Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused outputs can be disabled Output Features: • 2 - 0.7V current mode differential output pairs (HCSL) Key Specifications: • Cycle-to-cycle jitter < 50 ps • Output-to-output skew < 50 ps • PCIe Gen3 phase jitter < 1.0ps RMS Block Diagram OE0# OE1# SRC_IN SRC_IN# PLL_BW SMBDAT SMBCLK SPREAD COMPATIBLE PLL CONTROL LOGIC DIF_0 DIF_1 IREF IDT® Two Output Differential Buffer for PCIe Gen3 1 1667C—04/20/11 1 page 9DB233 Two Output Differential Buffer for PCIe Gen3 Datasheet Electrical Characteristics - Clock Input Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Input High Voltage - DIF_IN VIHDIF Differential inputs (single-ended measurement) Input Low Voltage - DIF_IN VILDIF Differential inputs (single-ended measurement) Input Common Mode Voltage - DIF_IN VCOM Common Mode Input Voltage Input Amplitude - DIF_IN Input Slew Rate - DIF_IN VSWING dv/dt Peak to Peak value Measured differentially Input Leakage Current IIN VIN = VDD , VIN = GND Input Duty Cycle dtin Measurement from differential wavefrom Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 1 Guaranteed by design and characterization, not 100% tested in production. 2Slew rate measured through +/-75mV window centered around differential zero MIN TYP 600 800 VSS - 300 300 300 0.4 -5 45 0 0 MAX 1150 UNITS NOTES mV 1 300 mV 1 1000 1450 8 5 55 125 mV mV V/ns uA % ps 1 1 1,2 1 1 1 Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate Slew rate matching Trf ∆Trf Scope averaging on Slew rate matching, Scope averaging on 0.6 2.5 4 V/ns 1, 2, 3 9.5 20 % 1, 2, 4 Voltage High Voltage Low VHigh VLow Statistical measurement on single-ended signal 660 740 850 using oscilloscope math function. (Scope averaging mV on) -150 8 150 1 1 Max Voltage Min Voltage Vmax Vmin Measurement on single ended signal using absolute value. (Scope averaging off) -300 760 -3 1150 mV 1 1 Vswing Vswing Scope averaging off 300 1506 mV 1, 2 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 378 550 mV 1, 5 Crossing Voltage (var) ∆-Vcross Scope averaging off 54 140 mV 1, 6 1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance). 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics - Current Consumption TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Supply Current IDD3.3OP All outputs active @100MHz, CL = Full load; Powerdown Current IDD3.3PD IDD3.3PDZ All diff pairs driven All differential pairs tri-stated 1Guaranteed by design and characterization, not 100% tested in production. 70 80 mA 1 N/A mA 1 N/A mA 1 IDT® Two Output Differential Buffer for PCIe Gen3 5 1667C—04/20/11 5 Page 9DB233 Two Output Differential Buffer for PCIe Gen3 SMBus Table: DEVICE ID Byte 4 Pin # Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 - Name Control Function Type R R R Device ID R = 06 Hex R R R R SMBus Table: Byte Count Register Byte 5 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - - - BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type RW Writing to this RW register will RW configure how RW many bytes will be RW read back, default RW is 06 = 6 bytes. RW RW 01 - - - - - - - - 01 -- -- -- -- -- -- -- -- Datasheet Default 0 0 0 0 0 1 1 0 Default 0 0 0 0 0 1 1 0 IDT® Two Output Differential Buffer for PCIe Gen3 11 1667C—04/20/11 11 Page

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