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9DBU0431 PDF даташит

Спецификация 9DBU0431 изготовлена ​​​​«IDT» и имеет функцию, называемую «4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB».

Детали детали

Номер произв 9DBU0431
Описание 4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
Производители IDT
логотип IDT логотип 

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9DBU0431 Даташит, Описание, Даташиты
4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0431
DATASHEET
Description
The 9DBU0431 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs; save 8 resistors compared to standard
HCSL outputs
45mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/software selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
vOE(3:0)#
4
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF3
DIF2
DIF1
DIF0
9DBU0431 REVISION C 04/22/15 1 ©2014 Integrated Device Technology, Inc.









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9DBU0431 Даташит, Описание, Даташиты
9DBU0431 DATASHEET
Pin Configuration
^vHIBW_BYPM_LOBW# 1
FB_DNC 2
FB_DNC# 3
VDDR1.5 4
CLK_IN 5
CLK_IN# 6
GNDR 7
GNDDIG 8
32 31 30 29 28 27 26 25
9DBU0431
epad is GND
9 10 11 12 13 14 15 16
24 vOE2#
23 DIF2#
22 DIF2
21 VDDA1.5
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor
(biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
OEx# Pin
DIFx
True O/P Comp. O/P
0 X X X Low Low
1
Running
0
X
Low Low
1
Running
1
0
Running
Running
1
Running
1
1
Low Low
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
PLL
Off
On1
On1
On1
Power Connections
PLL Operating Mode
Pin Number
VDD
GND
47
98
16, 25
15,20,26,30
21 20
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
Note: epad on this device is not electrically connected to the die.
It should be connected to ground for best thermal performance.
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
4 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
2
REVISION C 04/22/15









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9DBU0431 Даташит, Описание, Даташиты
9DBU0431 DATASHEET
Pin Descriptions
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin Name
^vHIBW_BYPM_LOBW#
FB_DNC
FB_DNC#
VDDR1.5
CLK_IN
CLK_IN#
GNDR
GNDDIG
VDDDIG1.5
SCLK_3.3
SDATA_3.3
vOE0#
DIF0
DIF0#
GND
VDDO1.5
vOE1#
DIF1
DIF1#
GNDA
VDDA1.5
DIF2
DIF2#
vOE2#
VDDO1.5
GND
DIF3
DIF3#
vOE3#
GND
^CKPWRGD_PD#
Type Pin Description
LATCHED IN
Trilevel input to select High BW, Bypass or Low
See PLL Operating Mode Table for Details.
BW mode.
DNC
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
DNC
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
PWR
1.5V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Analog Ground pin for the differential input (receiver)
GND Ground pin for digital circuitry
PWR 1.5V digital power (dirty power)
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin.
PWR Power supply for outputs, nominally 1.5V.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin for the PLL core.
PWR 1.5V power for the PLL core.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for outputs, nominally 1.5V.
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
32 ^SADR_tri
LATCHED IN Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
33 EPAD
GND Connect ePAD to ground.
REVISION C 04/22/15
3 4 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB










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