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9DBV0241 PDF даташит

Спецификация 9DBV0241 изготовлена ​​​​«IDT» и имеет функцию, называемую «2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer».

Детали детали

Номер произв 9DBV0241
Описание 2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer
Производители IDT
логотип IDT логотип 

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9DBV0241 Даташит, Описание, Даташиты
2-Output 1.8V PCIe Gen1-2-3 Zero Delay /
Fanout Buffer with Zo=100ohms
9DBV0241
DATASHEET
Description
The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 2 output enables for clock
management.
Recommended Application
1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
2 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF pairs
w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms (12k-20MHz)
Block Diagram
Features/Benefits
LP-HCSL outputs with Zo=100; saves 8 resistors
compared to standard HCSL output
35mW typical power consumption in PLL mode; minimal
power consumption
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/software selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface; works with legacy
controllers
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
9DBV0241 REVISION D 09/11/15 1 ©2015 Integrated Device Technology, Inc.









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9DBV0241 Даташит, Описание, Даташиты
9DBV0241 DATASHEET
Pin Configuration
FB_DNC# 1
VDDR1.8 2
CLK_IN 3
CLK_IN# 4
GNDR 5
GNDDIG 6
24 23 22 21 20 19
9DBV0241
epad is GND
7 8 9 10 11 12
18 DIF1#
17 DIF1
16 VDDA1.8
15 GNDA
14 DIF0#
13 DIF0
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull
down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
Power Management Table
CKPWRGD_PD#
0
CLK_IN
X
SMBus
OEx bit
X
OEx# Pin
X
DIFx
True O/P Comp. O/P
Low Low
1
Running
0
X
Low Low
1
Running
1
0
Running
Running
1
Running
1
1
Low Low
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
PLL
Off
On1
On1
On1
Power Connections
Pin Number
VDD
2
7
11,20
16
GND
5
6
10,21
15
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
Frequency Select Table
FSEL
Byte3 [4:3]
00 (Default)
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
SMBus Address
Address
1101101
+ Read/Write bit
x
2-OUTPUT 1.8V PCIE GEN1-2-3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS
2
REVISION D 09/11/15









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9DBV0241 Даташит, Описание, Даташиты
9DBV0241 DATASHEET
Pin Descriptions
Pin#
Pin Name
Type
Pin Description
Complement clock of differential feedback. The feedback output
1 FB_DNC#
DNC and feedback input are connected internally on this pin. Do not
connect anything to this pin.
2 VDDR1.8
PWR
1.8V power for differential input clock (receiver). This VDD should
be treated as an Analog power rail and filtered appropriately.
3 CLK_IN
IN True Input for differential reference clock.
4 CLK_IN#
IN Complementary Input for differential reference clock.
5 GNDR
GND Analog Ground pin for the differential input (receiver)
6 GNDDIG
GND Ground pin for digital circuitry
7 VDDDIG1.8
PWR 1.8V digital power (dirty power)
8 SCLK_3.3
IN Clock pin of SMBus circuitry, 3.3V tolerant.
9 SDATA_3.3
I/O Data pin for SMBus circuitry, 3.3V tolerant.
10 GND
GND Ground pin.
11 VDDO1.8
PWR Power supply for outputs, nominally 1.8V.
Active low input for enabling DIF pair 0. This pin has an internal pull-
12 vOE0#
IN down.
1 =disable outputs, 0 = enable outputs
13 DIF0
OUT Differential true clock output
14 DIF0#
OUT Differential Complementary clock output
15 GNDA
GND Ground pin for the PLL core.
16 VDDA1.8
PWR 1.8V power for the PLL core.
17 DIF1
OUT Differential true clock output
18 DIF1#
OUT Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-
19 vOE1#
IN down.
1 =disable outputs, 0 = enable outputs
20 VDDO1.8
PWR Power supply for outputs, nominally 1.8V.
21 GND
GND Ground pin.
Input notifies device to sample latched inputs and start up on first
22 ^CKPWRGD_PD#
IN
high assertion. Low enters Power Down Mode, subsequent high
assertions exit Power Down Mode. This pin has internal pull-up
resistor.
LATCHED Trilevel input to select High BW, Bypass or Low BW mode. This
23 ^vHIBW_BYPM_LOBW#
IN pin is biased to VDD/2 (Bypass mode) with internal pull up/pull down
resistors. See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and
24 FB_DNC
DNC feedback input are connected internally on this pin. Do not connect
anything to this pin.
25 epad
GND GND
NOTE: DNC indicates Do Not Connect anything to this pin.
REVISION D 09/11/15
3
2-OUTPUT 1.8V PCIE GEN1-2-3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS










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