9DBV0731 PDF даташит
Спецификация 9DBV0731 изготовлена «IDT» и имеет функцию, называемую «7-output 1.8V HCSL Fanout Buffer». |
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Детали детали
Номер произв | 9DBV0731 |
Описание | 7-output 1.8V HCSL Fanout Buffer |
Производители | IDT |
логотип |
17 Pages
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7-output 1.8V HCSL Fanout Buffer
9DBV0731
DATASHEET
Description
The 9DBV0731 is a member of IDT's Full-Featured PCIe
family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
PCIe Gen1-3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
• 7 - 1-200MHz Low-Power (LP) HCSL DIF pairs
• Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
• Additive cycle-to-cycle jitter <5ps
• Output-to-output skew < 60ps
• Additive phase jitter is <100fs RMS for PCIe Gen3
• Additive phase jitter <300fs rms (12kHz-20MHz @125MHz)
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
• LP-HCSL outputs; saves 14resistors and 24mm2 compared
to standard HCSL
• 41mW typical power consumption; elminates thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
• OE# pin for each output; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• SMBus-selectable features allow optimization to customer
requirements
• Slew rate for each output; allows tuning for various line
lengths
• Differential output amplitude; allows tuning for various
application environments
• 1MHz to 200MHz operating frequency
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• Device contains default configuration; SMBus interface not
required for device operation
• Space saving 40-pin 5x5mm VFQFPN; minimal board
space
` DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0731 REVISION D 03/28/16 1 ©2016 Integrated Device Technology, Inc.
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9DBV0731 DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSADR_tri 1
30 NC
vOE6# 2
29 vOE3#
DIF6 3
28 DIF3#
DIF6# 4
VDDR1.8 5
CLK_IN 6
CLK_IN# 7
9DBV0731
connect epad to
GND
27 DIF3
26 VDDIO
25 VDD1.8
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SADR
0
M
1
40-VFQFPN
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Dow n Resistor
5mm x 5mm 0.4mm pin pitch
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low Low
Low Low
Running Running
Low Low
Power Connections
VDD
Pin Number
VDDIO
5
11
16, 25, 31
12,17,26,32,39
GND
41
8
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
7-OUTPUT 1.8V HCSL FANOUT BUFFER
2
REVISION D 03/28/16
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9DBV0731 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 vSADR_tri
2 vOE6#
3 DIF6
4 DIF6#
5 VDDR1.8
6 CLK_IN
7 CLK_IN#
8 GNDDIG
9 SCLK_3.3
10 SDATA_3.3
11 VDDDIG1.8
12 VDDIO
13 vOE0#
14 DIF0
15 DIF0#
16 VDD1.8
17 VDDIO
18 DIF1
19 DIF1#
20 NC
21 vOE1#
22 DIF2
23 DIF2#
24 vOE2#
25 VDD1.8
26 VDDIO
27 DIF3
28 DIF3#
29 vOE3#
30 NC
31 VDD1.8
32 VDDIO
33 DIF4
34 DIF4#
35 vOE4#
36 DIF5
37 DIF5#
38 vOE5#
39 VDDIO
40 ^CKPWRGD_PD#
41 ePAD
PIN TYPE
DESCRIPTION
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
IN Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR
1.8V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.8V digital power (dirty power)
PWR Power supply for differential outputs
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
N/A No Connection.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
N/A No Connection.
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND Connect paddle to ground.
REVISION D 03/28/16
3 7-OUTPUT 1.8V HCSL FANOUT BUFFER
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Номер в каталоге | Описание | Производители |
9DBV0731 | 7-output 1.8V HCSL Fanout Buffer | IDT |
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