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PDF 9DBV0841 Data sheet ( Hoja de datos )
| Número de pieza | 9DBV0841 | |
| Descripción | 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER | |
| Fabricantes | IDT | |
| Logotipo |  |
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8-output 1.8V PCIe Gen1-3
Zero-Delay/Fan-out Buffer w/Zo=100ohms
9DBV0841
DATASHEET
Description
The 9DBV0841 is a 1.8V member of IDT's full featured PCIe
family. It has integrated output terminations providing
Zo=100 for direct connection for 100 transmission lines.
The device has 8 output enables for clock management and 3
selectable SMBus addresses.
Recommended Application
SSD, microServers, WLAN Access points
Output Features
• 8 – 1-200Hz Low-Power (LP) HCSL DIF pairs
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
• LP-HCSL outputs save 32 resistors; minimal board space
and BOM cost
• 62mW typical power consumption in PLL mode; eliminates
thermal concerns
• Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 48-pin 6x6mm VFQFPN; minimal board
space
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(7:0)#
8
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SS
Compatible
PLL
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0841 APRIL 28, 2016
1 ©2016 Integrated Device Technology, Inc.
1 page  
9DBV0841 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0841. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
1.8V Supply Voltage
VDDxx
Applies to VDD, VDDA and VDDIO
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Input Common Mode
Voltage - DIF_IN
Input Swing - DIF_IN
VCOM
VSWING
Common Mode Input Voltage
Differential value
150
300
Input Slew Rate - DIF_IN dv/dt
Measured differentially
0.4
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
TYP MAX UNITS NOTES
1000
mV
1
mV 1
8 V/ns 1,2
5 uA
55 % 1
125 ps 1
APRIL 28, 2016
5
8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
5 Page 
9DBV0841 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
Bit 7
RID3
Bit 6
Bit 5
RID2
RID1
Revision ID
Bit 4
RID0
Bit 3
VID3
Bit 2
Bit 1
VID2
VID1
VENDOR ID
Bit 0
VID0
Type
R
R
R
R
R
R
R
R
01
A rev = 0000
0001 = IDT
Default
0
0
0
0
0
0
0
1
SMBus Table: Device Type/Device ID
Byte 6
Name
Bit 7
Device Type1
Bit 6
Device Type0
Bit 5
Device ID5
Bit 4
Device ID4
Bit 3
Device ID3
Bit 2
Device ID2
Bit 1
Device ID1
Bit 0
Device ID0
Control Function
Device Type
Device ID
Type
R
R
R
R
R
R
R
R
01
00 = FGx, 01 = DBx,
10 = DMx, 11= Reserved
001000 binary or 08 hex
Default
0
1
0
0
1
0
0
0
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
Bit 4
BC4
Bit 3
BC3
Bit 2
BC2
Bit 1
BC1
Bit 0
BC0
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
0
1
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW = 8 bytes.
RW
Default
0
0
0
0
1
0
0
0
APRIL 28, 2016
11
8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 9DBV0841.PDF ] | |
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