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9DBV0941 PDF даташит

Спецификация 9DBV0941 изготовлена ​​​​«IDT» и имеет функцию, называемую «9-output 1.8V HCSL Fanout Buffer».

Детали детали

Номер произв 9DBV0941
Описание 9-output 1.8V HCSL Fanout Buffer
Производители IDT
логотип IDT логотип 

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9DBV0941 Даташит, Описание, Даташиты
9-output 1.8V HCSL Fanout Buffer
w/Zo=100ohms
9DBV0941
DATASHEET
Description
The 9DBV0941 is a member of IDT's Full-Featured PCIe
family. The device has 9 output enables for clock
management, and 3 selectable SMBus addresses. It has
integrated terminations for direct connection to 100ohm
transmission lines.
Recommended Application
PCIe Gen1-3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
9 - 1-200MHz Low-Power (LP) HCSL DIF pairs w/ZO=100
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
Additive cycle-to-cycle jitter <5ps
Output-to-output skew < 60ps
Additive phase jitter is <100fs rms for PCIe Gen3
Additive phase jitter <300fs rms (12kHz-20MHz @125MHz)
Block Diagram
Features/Benefits
100ohm direct connect; saves 36 resistors and 62mm2
compared to standard HCSL
53mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features allow optimization to customer
requirements
Slew rate for each output; allows tuning for various line
lengths
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0941 REVISION C 03/28/16 1 ©2016 Integrated Device Technology, Inc.









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9DBV0941 Даташит, Описание, Даташиты
9DBV0941 DATASHEET
Pin Configuration
vSADR_tri 1
vOE8# 2
DIF8 3
DIF8# 4
VDDR1.8 5
CLK_IN 6
CLK_IN# 7
GNDR 8
GNDDIG 9
SCLK_3.3 10
SDATA_3.3 11
VDDDIG1.8 12
48 47 46 45 44 43 42 41 40 39 38 37
9DBV0941
connect epad to
ground
13 14 15 16 17 18 19 20 21 22 23 24
36 DIF5#
35 DIF5
34 vOE4#
33 DIF4#
32 DIF4
31 VDDIO
30 VDD1.8
29 GND
28 vOE3#
27 DIF3#
26 DIF3
25 vOE2#
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND pull down resistor
(biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
Power Connections
Pin Number
VDD
VDDIO
5
12
20,30,31,38
13,21,31,39,
47
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
GND
8
9
Description
Input
receiver
analog
Digital Power
22,29,40 DIF outputs
DIFx
True O/P Comp. O/P
Low Low
Low Low
Running
Running
Low Low
9-OUTPUT 1.8V HCSL FANOUT BUFFER W/ZO=100OHMS
2
REVISION C 03/28/16









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9DBV0941 Даташит, Описание, Даташиты
Pin Descriptions
PIN #
PIN NAME
1 vSADR_tri
2 vOE8#
3 DIF8
4 DIF8#
5 VDDR1.8
6 CLK_IN
7 CLK_IN#
8 GNDR
9 GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG1.8
13 VDDIO
14 vOE0#
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
20 VDD1.8
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
26 DIF3
27 DIF3#
28 vOE3#
29 GND
30 VDD1.8
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
37 vOE5#
38 VDD1.8
39 VDDIO
REVISION C 03/28/16
9DBV0941 DATASHEET
TYPE
DESCRIPTION
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
IN Active low input for enabling DIF pair 8. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR 1.8V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Analog Ground pin for the differential input (receiver)
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.8V digital power (dirty power)
PWR Power supply for differential outputs
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin.
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
3 9-OUTPUT 1.8V HCSL FANOUT BUFFER W/ZO=100OHMS










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