9DBL08 PDF даташит
Спецификация 9DBL08 изготовлена «IDT» и имеет функцию, называемую «8-output 3.3V PCIe Zero-Delay Buffer». |
|
Детали детали
Номер произв | 9DBL08 |
Описание | 8-output 3.3V PCIe Zero-Delay Buffer |
Производители | IDT |
логотип |
19 Pages
No Preview Available ! |
8-output 3.3V PCIe Zero-Delay Buffer
9DBL08
Description
The 9DBL08 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DBL08 supports PCIe
Gen1-4 Common Clocked (CC) and PCIe Separate
Reference Independent Spread (SRIS) systems. It offers a
choice of integrated output terminations providing direct
connection to 85Ω or 100Ω transmission lines. The
9DBL08P1 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
• 8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
• 9DBL0841 default ZOUT = 100
• 9DBL0851 default ZOUT = 85
• 9DBL08P1 factory programmable defaults
• Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
• PCIe Gen1-2-3-4 CC compliant in ZDB mode
• PCIe Gen2 SRIS compliant in ZDB mode
• Supports PCIe Gen2-3 SRIS in fan-out mode
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew < 50ps
• Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
• Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Block Diagram
DATASHEET
Features/Benefits
• Direct connection to 100 (0841) or 85 (0851)
transmission lines; saves 32 resistors compared to
standard PCIe devices
• 211mW typical power consumption (PLL [email protected]);
eliminates thermal concerns
• VDDIO allows 35% power savings at optional 1.05V;
maximum power savings
• SMBus-selectable features allows optimization to customer
requirements:
• control input polarity
• control input pull up/downs
• slew rate for each output
• differential output amplitude
• output impedance for each output
• 50, 100, 125MHz operating frequency
• Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• Spread Spectrum tolerant; allows reduction of EMI
• Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device operation
• Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF3.3
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DBL08 REVISION D 08/16/16
1 ©2016 Integrated Device Technology, Inc.
No Preview Available ! |
9DBL08 DATASHEET
Pin Configuration
vSADR_tri 1
^vHIBW_BYPM_LOBW# 2
48 47 46 45 44 43 42 41 40 39 38 37
36 DIF5#
35 DIF5
FB_DNC 3
FB_DNC# 4
VDDR3.3 5
CLK_IN 6
CLK_IN# 7
GNDR 8
9DBL0841/51/P1
epad is GND
34 vOE4#
33 DIF4#
32 DIF4
31 VDDIO
30 VDDA3.3
29 GNDA
GNDDIG 9
SCLK_3.3 10
SDATA_3.3 11
VDDDIG3.3 12
28 vOE3#
27 DIF3#
26 DIF3
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to
transition from 2.1V to 3.135V in <300usec.
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
DIFx
OEx# Pin True O/P Comp. O/P
0
X
X
X
Low1
Low1
1
Running
0
X
Low1
Low1
1
Running
1
0 Running Running
1
Running
1
1
Low1
Low1
1. The output state is set by B11[1:0] (Low/Low default)
2. If Bypass mode is selected, the PLL will be off, and outputs will be running.
PLL
Off
On2
On2
On2
Power Connections
Pin Number
VDD
VDDIO
5
12
20,31,38
30
13,21,31,
39,47
GND
8
9
Description
Input
receiver
analog
Digital Power
22, 29,40,49 DIF outputs
29 PLL Analog
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
2
REVISION D 08/16/16
No Preview Available ! |
9DBL08 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
1 vSADR_tri
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode. This pin is biased
2 ^vHIBW_BYPM_LOBW#
IN
to VDD/2 (Bypass mode) with internal pull up/pull down resistors. See PLL
Operating Mode Table for Details.
3 FB_DNC
DNC
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
4 FB_DNC#
DNC
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
5 VDDR3.3
6 CLK_IN
7 CLK_IN#
8 GNDR
9 GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG3.3
13 VDDIO
14 vOE0#
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
20 VDD3.3
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
26 DIF3
27 DIF3#
28 vOE3#
29 GNDA
30 VDDA3.3
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
37 vOE5#
38 VDD3.3
39 VDDIO
PWR
IN
IN
GND
GND
IN
I/O
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
GND
OUT
OUT
IN
OUT
OUT
IN
GND
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
3.3V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling output 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 3.3V
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
3.3V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
Power supply for differential outputs
REVISION D 08/16/16
3 8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
Скачать PDF:
[ 9DBL08.PDF Даташит ]
Номер в каталоге | Описание | Производители |
9DBL02 | 2-output 3.3V PCIe Zero-Delay Buffer | IDT |
9DBL04 | 4-output 3.3V PCIe Zero-delay Buffer | IDT |
9DBL06 | 6-output 3.3V PCIe Zero-Delay Buffer | IDT |
9DBL08 | 8-output 3.3V PCIe Zero-Delay Buffer | IDT |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |