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9DBV0531 PDF даташит

Спецификация 9DBV0531 изготовлена ​​​​«IDT» и имеет функцию, называемую «5-output 1.8V HCSL Fanout Buffer».

Детали детали

Номер произв 9DBV0531
Описание 5-output 1.8V HCSL Fanout Buffer
Производители IDT
логотип IDT логотип 

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9DBV0531 Даташит, Описание, Даташиты
5-output 1.8V HCSL Fanout Buffer
9DBV0531
DATASHEET
Description
The 9DBV0531 is a member of IDT's Full-Featured PCIe
family. The device has 5 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
PCIe Gen1-3 clock distribution in Storage, Networking,
Computing, Consumer
Output Features
5 - 1-200MHz Low-Power (LP) HCSL DIF pairs
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
Additive cycle-to-cycle jitter <5ps
Output-to-output skew < 50ps
Additive phase jitter is <100fs rms for PCIe Gen3
Additive phase jitter <300fs rms (12kHz-20MHz @125MHz)
Features/Benefits
LP-HCSL outputs; save 10 resistors and 17mm2 compared
to standard HCSL
50mW typical power consumption; eliminates thermal
concerns
OE# pin for each output; support DIF power management
HCSL differential input; can be driven by common clock
sources
Spread Spectrum tolerant; allows reduction of EMI
SMBus-selectable features allow optimization to customer
requirements
Slew rate for each output; allows tuning for various line
lengths
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Block Diagram
vOE(4:0)#
5
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0531 REVISION E 05/23/16 1 ©2016 Integrated Device Technology, Inc.









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9DBV0531 Даташит, Описание, Даташиты
9DBV0531 DATASHEET
Pin Configuration
vOE4# 1
DIF4 2
DIF4# 3
VDDR1.8 4
CLK_IN 5
CLK_IN# 6
GNDR 7
GNDDIG 8
32 31 30 29 28 27 26 25
9DBV0531
connect
epad to GND
9 10 11 12 13 14 15 16
24 vOE2#
23 DIF2#
22 DIF2
21 VDDO1.8
20 GND
19 DIF1#
18 DIF1
17 vOE1#
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull
down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low Low
Low Low
Running
Running
Low Low
Power Connections
Pin Number
VDD
GND
47
98
16, 25
15,20,26,30
21 20
Description
Input receiver analog
Digital Power
DIF outputs
Analog
5-OUTPUT 1.8V HCSL FANOUT BUFFER
2
REVISION E 05/23/16









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9DBV0531 Даташит, Описание, Даташиты
9DBV0531 DATASHEET
Pin Descriptions
Pin# Pin Name
1 vOE4#
2 DIF4
3 DIF4#
4 VDDR1.8
5 CLK_IN
6 CLK_IN#
7 GNDR
8 GNDDIG
9 VDDDIG1.8
10 SCLK_3.3
11 SDATA_3.3
12 vOE0#
13 DIF0
14 DIF0#
15 GND
16 VDDO1.8
17 vOE1#
18 DIF1
19 DIF1#
20 GND
21 VDDO1.8
22 DIF2
23 DIF2#
24 vOE2#
25 VDDO1.8
26 GND
27 DIF3
28 DIF3#
29 vOE3#
30 GND
31 ^CKPWRGD_PD#
32 ^SADR_tri
33 ePAD
Type Pin Description
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT
PWR
IN
IN
Differential Complementary clock output
1.8V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
GND
GND
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
PWR
IN
1.8V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
IN
OUT
OUT
Data pin for SMBus circuitry, 3.3V tolerant.
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
GND
PWR
Ground pin.
Power supply for outputs, nominally 1.8V.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT
OUT
Differential true clock output
Differential Complementary clock output
GND
PWR
Ground pin.
Power supply for outputs, nominally 1.8V.
OUT
OUT
IN
PWR
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for outputs, nominally 1.8V.
GND
OUT
Ground pin.
Differential true clock output
OUT
IN
GND
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
LATCHED IN
Tri-level latch to select SMBus Address. It has an internal 120Kohm pull down
resistor. See SMBus Address Selection Table.
GND Connect epad to ground.
REVISION E 05/23/16
3 5-OUTPUT 1.8V HCSL FANOUT BUFFER










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