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PDF 74ALVCH32245 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH32245 | |
| Descripción | LOW VOLTAGE CMOS 32-BIT BUS TRANSCEIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74ALVCH32245
LOW VOLTAGE CMOS 32-BIT BUS TRANSCEIVER
(3-STATE) WITH 3.6V TOLERANTAT INPUTS AND OUTPUTS
s 3.6V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED:
tPD = 3.0ns (MAX.) at VCC = 3.0 to 3.6V
tPD = 3.7ns (MAX.) at VCC = 2.3 to 2.7V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
|IOH| = IOL = 8mA (MIN) at VCC = 2.3V
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 32245
s BUS HOLD PROVIDED ON BOTH SIDE
s LATCH-UP PERFORMANCE EXCEEDS
300mA
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74ALVCH32245 is a low voltage CMOS
32-BIT BUS TRANSCEIVER (3-STATE)
fabricated with sub-micron silicon gate and
five-layer metal wiring C2MOS technology. It is
ideal for 1.65 to 3.6 V applications; it can be
interfaced to 3.6V signal enviroment for both
inputs and outputs.
LOGIC DIAGRAM
LFBGA96
(Top and Bottom view)
ORDER CODES
PACKAGE
TRAY
T&R
LFBGA96 74ALVCH32245LB 74ALVCH32245LBR
This IC is intended for two-ways asynchronous
communication between data buses: the direction
of data trasmission is determined by DIR input.
Any nG contol output governs eight BUS
TRANSCEIVERS. Output Enable input (nG) tied
together gives full 32-bit operation. When nG is
LOW, the output are enabled. When nG is HIGH,
the output are in high impedance state so that the
buses are effectively isolated. Bus hold on data
inputs is provided in order to eliminate the need for
external pull-up or pull-down resistor.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2002
1/9
1 page  
74ALVCH32245
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
tPLH tPHL Propagation Delay Time
tPZL tPZH Output Enable Time
tPLZ tPHZ Output Disable Time
Test Condition
VCC
(V)
2.3 to 2.7
2.7
3.0 to 3.6
2.3 to 2.7
2.7
3.0 to 3.6
2.3 to 2.7
2.7
3.0 to 3.6
CL
(pF)
30
50
50
30
50
50
30
50
50
Value
-40 to 85 °C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
3.7
3.6
3.0
5.7
5.4
4.4
5.2
4.6
4.1
Unit
ns
ns
ns
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25 °C
Min. Typ. Max.
Unit
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(note 1)
3.3
3.3
2.5
3.3
VI = 0V or VCC
VI = 0V or VCC
fIN = 10MHz
VI = 0V or VCC
4 pF
8 pF
22
pF
28
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/32 (per
circuit)
5/9
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH32245.PDF ] | |
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