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PDF N01S830BA Data sheet ( Hoja de datos )
| Número de pieza | N01S830BA | |
| Descripción | 1 Mb Ultra-Low Power Serial SRAM | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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N01S830HA, N01S830BA
1 Mb Ultra-Low Power
Serial SRAM
Standard SPI Interface and Multiplex
DUAL and QUAD Interface
Overview
The ON Semiconductor serial SRAM family includes several
integrated memory devices including this 1 Mb serially accessed
Static Random Access Memory, internally organized as 128 K words
by 8 bits. The devices are designed and fabricated using
ON Semiconductor’s advanced CMOS technology to provide both
high-speed performance and low power. The devices operate with a
single chip select (CS) input and use a simple Serial Peripheral
Interface (SPI) protocol. In SPI mode, a single data-in (SI) and
data-out (SO) line is used along with the clock (SCK) to access data
within the device. In DUAL mode, two multiplexed data-in/data-out
(SIO0-SIO1) lines are used and in QUAD mode, four multiplexed
data-in/data-out (SIO0-SIO3) lines are used with the clock to access
the memory. The devices can operate over a wide temperature range of
−40°C to +85°C (+125°C for E−Temp) and are available in a 8-lead
TSSOP package. The N01S830xA device has two different variations,
a HOLD version that allows communication to the device to be paused
and a battery back-up (BBU) version to be used with a battery to retain
data when power is lost.
Features
• Power Supply Range: 2.5 to 5.5 V
• Very Low Typical Standby Current < 4 mA at +85°C
• Very Low Operating Current < 10 mA
• Simple Serial Interface
♦ Single-bit SPI Access
♦ DUAL-bit and QUAD-bit SPI-like Access
• Flexible Operating Modes
♦ Word Mode
♦ Page Mode
♦ Burst Mode (Full Array)
• High Frequency Read and Write Operation
♦ Clock Frequency up to 20 MHz
• Functional Options
♦ HOLD Pin for Pausing Operation
♦ VBAT Pin for Battery−Back up
• Built-in Write Protection (CS High)
• High Reliability
♦ Unlimited Write Cycles
• Temperature Ranges Supported
♦ Industrial (I): TA = −40°C to +85°C
♦ Automotive (E): TA = −40°C to +125°C
• These Devices are Pb−Free and are RoHS Compliant
♦ Green TSSOP
www.onsemi.com
TSSOP8 3x4.4
CASE 948BH
PACKAGE CONFIGURATION
CS
SO / SIO1
NC / SIO2
VSS
18
27
36
45
HOLD Version
VCC
HOLD / SIO3
SCK
SI / SIO0
CS
SO / SIO1
NC
VSS
18
27
36
45
BBU Version
VCC
VBAT
SCK
SI / SIO0
ORDERING INFORMATION
Device
Package
Shipping†
N01S830HAT22I
N01S830BAT22I
N01S830HAT22IT
N01S830BAT22IT
TSSOP−8
(Pb−Free)
100 Units / Tube
TSSOP−8
(Pb−Free)
3000 / Tape
& Reel
N01S830HAT22E
N01S830BAT22E
TSSOP−8
(Pb−Free)
100 Units / Tube
N01S830HAT22ET TSSOP−8
N01S830BAT22ET (Pb−Free)
3000 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 2
1
Publication Order Number:
N01S830HA/D
1 page  
N01S830HA, N01S830BA
CS
SCK
012345
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Instruction
24−bit address
Data out
SIO[1:0] C3 C2 C1 C0 A11 A10 A3 A2 A1 A0 X X X X H0 H0 L0 L0 H1 H1 L1 L1
MSB
MSB
Notes:
C[3:0] = 03h
H0 = 2 high order bits of data byte 0
L0 = 2 low order bits of data byte 0
H1 = 2 high order bits of data byte 1
L1 = 2 low order bits of data byte 1
Figure 4. DUAL Read Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Instruction
24−bit address
Data out
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0 X X H0 L0 H1 L1 H2 L2 H3 L3
MSB
MSB
Notes:
C[1:0] = 03h
H0 = 4 high order bits of data byte 0
L0 = 4 low order bits of data byte 0
H1 = 4 high order bits of data byte 1
L1 = 4 low order bits of data byte 1
Figure 5. QUAD Read Sequence
Write Operation
The serial SRAM WRITE is selected by enabling CS low.
First, the 8-bit WRITE instruction is transmitted to the
device followed by the 24-bit address with the 7 MSBs being
don’t care. After the WRITE instruction and addresses are
sent, the data to be stored in memory is shifted in on the SI
pin.
If operating in page mode, after the initial word of data is
shifted in, additional data words can be written as long as the
address requested is sequential on the same page. Simply
write the data on SI pin and continue to provide clock pulses.
The internal address pointer is automatically incremented to
the next higher address on the page after each word of data
is written in. This can be continued for the entire page length
of 32 words long. At the end of the page, the addresses
pointer will be wrapped to the 0 word address within the
page and the operation can be continuously looped over the
32 words of the same page. The new data will replace data
already stored in the memory locations.
If operating in burst mode, after the initial word of data is
shifted in, additional data words can be written to the next
sequential memory locations by continuing to provide clock
pulses. The internal address pointer is automatically
incremented to the next higher address after each word of
data is read out. This can be continued for the entire array
and when the highest address is reached, 1FFFFh, the
address counter wraps to the address 00000h. This allows
the burst write cycle to be continued indefinitely. Again, the
new data will replace data already stored in the memory
locations.
All WRITE operations are terminated by pulling CS high.
www.onsemi.com
5
5 Page 
N01S830HA, N01S830BA
CS
SCK
tCSS
tSU
tR
tHD
SI MSB in
SO
tF tCSH
LSB in
High−Z
Figure 16. SPI Input Timing
tCSD
tCLD
tSCS
CS
SCK
SO
SI
tLO tHI
tCSH
tV
MSB out
Don’t Care
Figure 17. SPI Output Timing
LSB out
tDIS
CS
SCK
SO n+2
SI n+2
tHS tHS tHH
tHH
n+1 n High−Z
tHZ
n+1 n Don’t Care
tHV
n n−1
tSU
n n−1
HOLD
Figure 18. SPI Hold Timing
www.onsemi.com
11
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| PDF Descargar | [ Datasheet N01S830BA.PDF ] | |
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