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N24C02 PDF даташит

Спецификация N24C02 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «I2C CMOS Serial EEPROM».

Детали детали

Номер произв N24C02
Описание I2C CMOS Serial EEPROM
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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N24C02 Даташит, Описание, Даташиты
N24C02, N24C04, N24C08,
N24C16
2-Kb, 4-Kb, 8-Kb and 16-Kb
I2C CMOS Serial EEPROM
Description
The N24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
respectively CMOS Serial EEPROM devices organized internally as
16/32/64 and 128 pages respectively of 16 bytes each. All devices
support the Standard (100 kHz), Fast (400 kHz) and Fast−Plus
(1 MHz) I2C protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
N24C02, four N24C04, two N24C08 and one N24C16 device on the
same bus.
Features
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V / 1.6 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Fast Write Time (4 ms max)
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low power CMOS Technology
More than 1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Automotive Grade 1 Temperature Range
US 8−Lead Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONFIGURATION
N24C__
16 / 08 / 04 / 02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
US8 (U) (Top View)
www.onsemi.com
US8
U SUFFIX
CASE 493
MARKING DIAGRAM
8
XX MG
G
1
XX = Specific Device Code*
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
* See Ordering Information section for the
Specific Device Marking Code
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 1
1
Publication Order Number:
N24C02/D









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N24C02 Даташит, Описание, Даташиты
N24C02, N24C04, N24C08, N24C16
SCL
A2, A1, A0
WP
VCC
N24Cxx
SDA
VSS
Figure 1. Functional Symbol
Table 1. PIN FUNCTION
Pin Name
Function
A0, A1, A2
Device Address Input
SDA
Serial Data Input/Output
SCL Serial Clock Input
WP Write Protect Input
VCC Power Supply
VSS Ground
NC No Connect
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
°C
Voltage on any pin with respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2
and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of VCC.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min Units
NEND (Note 2)
Endurance
TDR (Note 2)
Data Retention
2. TA = 25°C
3. A Write Cycle refers to writing a Byte or a Page.
1,000,000
100
Write Cycles (Note 3)
Years
Table 4. D.C. OPERATING CHARACTERISTICS
(VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min Max Units
ICCR
Read Current
Read, fSCL = 1 MHz
0.3 mA
ICCW
Write Current
Write
0.5 mA
ISB Standby Current
All I/O Pins at GND or VCC
TA = −40°C to +85°C
1 mA
TA = −40°C to +125°C
2
IL I/O Pin Leakage
Pin at GND or VCC
2 mA
VIL1 Input Low Voltage
2.2 V VCC 5.5 V
−0.5
0.3 VCC
V
VIL2 Input Low Voltage
1.6 V VCC < 2.2 V
−0.5
0.2 VCC
V
VIH1
Input High Voltage
2.2 V VCC 5.5 V
0.7 VCC
VCC + 0.5
V
VIH2
Input High Voltage
1.6 V VCC < 2.2 V
0.8 VCC
VCC + 0.5
V
VOL1
Output Low Voltage
VCC 2.2 V, IOL = 6.0 mA
0.4 V
VOL2
Output Low Voltage
VCC < 2.2 V, IOL = 2.0 mA
0.2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*VCC(min) = 1.6 V for Read operations, TA = −20°C to +85°C.
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N24C02 Даташит, Описание, Даташиты
N24C02, N24C04, N24C08, N24C16
Table 5. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max Units
CIN (Note 4) SDA I/O Pin Capacitance
VIN = 0 V
8 pF
CIN (Note 4) Input Capacitance (other pins)
VIN = 0 V
6 pF
IWP, IA
(Note 5)
WP Input Current, Address Input
Current (A0, A1, A2)
VIN < VIH, VCC = 5.5 V
VIN < VIH, VCC = 3.3 V
50 mA
35
VIN < VIH, VCC = 1.7 V
25
VIN > VIH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
*VCC(min) = 1.6 V for Read operations, TA = −20°C to +85°C.
Table 6. A.C. CHARACTERISTICS
(VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 6)
Standard
Fast
Fast−Plus
Symbol
FSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR (Note 7)
tF (Note 7)
tSU:STO
tBUF
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between
STOP and START
Min
4
4.7
4
4.7
0
250
4
4.7
Max
100
1,000
300
Min
0.6
1.3
0.6
0.6
0
100
0.6
1.3
Max
400
300
300
Min
0.26
0.50
0.26
0.26
0
50
0.26
0.5
Max
1,000
120
120
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
tAA SCL Low to Data Out Valid 3.5 0.9
0.45 ms
tDH (Note 7) Data Out Hold Time
100
100
50
ns
Ti (Note 7)
Noise Pulse Filtered at SCL
and SDA Inputs
50
50
50 ns
tSU:WP
WP Setup Time
0
0
tHD:WP
WP Hold Time
2.5
2.5
tWR Write Cycle Time
44
tPU (Notes 7, 8) Power-up to Ready Mode
0.35 0.35
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
*VCC(min) = 1.6 V for Read operations, TA = −20°C to +85°C.
0
1
ms
ms
4 ms
0.35 ms
Table 7. A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC for VCC 2.2 V
0.15 x VCC to 0.85 x VCC for VCC < 2.2 V
Input Rise and Fall Times
50 ns
Input Reference Levels
Output Reference Levels
Output Load
0.3 x VCC, 0.7 x VCC
0.3 x VCC, 0.7 x VCC
Current Source: IOL = 6 mA (VCC 2.2 V); IOL = 2 mA (VCC < 2.2 V); CL = 100 pF
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