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N34C04 PDF даташит

Спецификация N34C04 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «4-Kb Serial SPD EEPROM».

Детали детали

Номер произв N34C04
Описание 4-Kb Serial SPD EEPROM
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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N34C04 Даташит, Описание, Даташиты
N34C04
4-Kb Serial SPD EEPROM
for DDR4 DIMM
Description
The N34C04 is a 4−Kb serial EEPROM, which implements the
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD)
specification for DDR4 DIMMs and supports the Standard (100 kHz),
Fast (400 kHz) and Fast Plus (1 MHz) I2C protocols.
One of the two available 2−Kb EEPROM banks (referred to as SPD
pages in the EE1004−v specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb EEPROM blocks can be Write
Protected by software command.
Features
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD) Compliant
Temperature Range: −40°C to +125°C
Supply Range: 1.7 V − 3.6 V
I2C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Low Power CMOS Technology
2 x 3 x 0.5 mm UDFN Package
These Devices are Pb−Free and are RoHS Compliant
VCC
SCL
A2, A1, A0
WP
N34C04
SDA
VSS
Figure 1. Functional Symbol
www.onsemi.com
1
UDFN8
MU3 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A0 1
A1
(Top View)
A2
VSS
VCC
WP
SCL
SDA
UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
MARKING DIAGRAM
D2U
AZZ
YM
G
UDFN8
D2U
A
ZZ
Y
M
G
= Specific Device Code
= Assembly Location Code
= Assembly Lot Number (Last Two Digits)
= Production Year (Last Digit)
= Production Month (1 − 9, O, N, D)
= Pb−Free Package
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
SDA
SCL
WP
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
VCC
VSS
DAP
Power Supply
Ground
Backside Exposed DAP at VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 0
1
Publication Order Number:
N34C04/D









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N34C04 Даташит, Описание, Даташиты
N34C04
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Operating Temperature
−45 to +130
°C
Storage Temperature
−65 to +150
°C
Voltage on any pin (except A0) with respect to Ground (Note 1)
−0.5 to +6.5
V
Voltage on pin A0 with respect to Ground
−0.5 to +10.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level for SWP
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND (Note 2)
Endurance
TDR Data Retention
2. Page Mode, VCC = 2.5 V, 25°C
Min
1,000,000
100
Units
Write Cycles
Years
Table 3. THERMAL CHARACTERISTICS (Note 3)
Parameter
Test Conditions/Comments
Max Unit
Thermal Resistance qJA
Junction−to−Ambient (Still Air)
92 °C/W
3. Power Dissipation is defined as PJ = (TJ − TA)/qJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 4. D.C. OPERATING CHARACTERISTICS (Vcc = 1.7 V to 3.6 V, TA = −40°C to +125°C, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min Max Units
ICCR
ICCW
ISB
Read Current
Write Current
Standby Current
Read, fSCL = 400 kHz or 1 MHz
Write, during tWR (Note 4)
All I/O Pins at
GND or Vcc
Vcc < 2.2 V
Vcc 2.2 V
1 mA
1 mA
1 mA
2
IL I/O Pin Leakage
Pin at GND or VCC
2 mA
VIL Input Low Voltage
−0.5 0.3*Vcc
V
VIH Input High Voltage
0.7*Vcc VCC + 0.5
V
VOL1
Output Low Voltage
VCC 2.2 V, IOL = 20 mA
0.4 V
VOL2
Output Low Voltage
VCC < 2.2 V, IOL = 6.0 mA
0.2 V
VPOR+
Power On Reset Threshold
(Note 4)
1.3 V
VPOR−
Power Off Reset Threshold
(Note 4)
0.8 V
4. Tested initially and after a design or process change that affects this parameter
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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N34C04 Даташит, Описание, Даташиты
N34C04
Table 5. A.C. CHARACTERISTICS (Note 6) VCC = 1.7 V to 3.6 V, TA = −40°C to +125°C, unless otherwise specified.
Standard
VCC = 1.7 V − 3.6 V
Fast
VCC = 1.7 V − 3.6 V
Fast−Plus
VCC = 2.2 V − 3.6 V
Symbol
Parameter
Min Max Min Max Min Max
Units
FSCL (Note 5) Clock Frequency
10
100
10
400
10
1,000
kHz
tHD:STA
START Condition Hold Time
4
0.6 0.26 ms
tLOW
Low Period of SCL Clock
4.7
1.3 0.50 ms
tHIGH
High Period of SCL Clock
4
0.6 0.26 ms
tSU:STA
START Condition Setup Time
4.7
0.6 0.26 ms
tHD:DI
Data In Hold Time
0
0
0 ms
tSU:DAT
Data In Setup Time
250
100
50
ns
tR (Note 7)
SDA and SCL Rise Time
1,000
300
120 ns
tF (Note 7)
SDA and SCL Fall Time
300 300 120 ns
tSU:STO
STOP Condition Setup Time
4
0.6 0.26 ms
tBUF Bus Free Time Between
4.7
1.3
0.5
ms
STOP and START
tHD:DAT
Data Out Hold Time
200 3450 200
900
0
350 ns
Ti (Note 7)
Noise Pulse Filtered at SCL
50
50
50 ns
and SDA Inputs
tSU:WP
WP Setup Time
0
0
0 ms
tHD:WP
WP Hold Time
2.5
2.5
1
ms
tWR Write Cycle Time
4 4 4 ms
tINIT (Notes 7, 8) Power-up to Ready Mode
0.5 0.5 0.5 ms
tPOFF (Note 9) Warm power cycle off time
0.2
0.2
0.2 ms
tTIMEOUT (Note 10) Detect clock low timeout
25 35 25 35 25 35 ms
5. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency is limited only by the SMBus
time−out. The device also meets the Fast and Standard I2C specifications, except that Ti and tDH are shorter, as required by the 1 MHz Fast
Plus protocol.
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tINIT is the delay between the Power−On Reset threshold (VPOR+) and the device is ready to accept commands.
9. Power−Off delay to ensure a proper Reset when the VCC drops below VPOR−
10. A timeout condition can only be ensured if SCL is driven low for tTIMEOUT(Max) or longer; then, N34C04 is reset and ready to receive a new
START condition. N34C04 does not reset if SCL is driven low for less than tTIMEOUT(Min). The interface will reset itself and will release the
SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out count takes place when SCL is low in the time interval between
START and STOP.
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
0.2 x VCC to 0.8 x VCC
50 ns
Input Reference Levels
Output Reference Levels
Output Load
0.3 x VCC, 0.7 x VCC
0.3 x VCC, 0.7 x VCC
Current Source: IOL = 6 mA; CL = 100 pF
Table 7. PIN CAPACITANCE (TA = 25°C, VCC = 3.6 V, f = 1 MHz)
Symbol
Parameter
Test Conditions/Comments Min Max Unit
CIN SDA, Pin Capacitance
Input Capacitance (other pins)
VIN = 0
VIN = 0
8 pF
6 pF
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N34C044-Kb Serial SPD EEPROMON Semiconductor
ON Semiconductor

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