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PDF NCN8025 Data sheet ( Hoja de datos )
| Número de pieza | NCN8025 | |
| Descripción | Compact SMART CARD Interface IC | |
| Fabricantes | ON Semiconductor | |
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NCN8025 / NCN8025A
Compact SMART CARD
Interface IC
The NCN8025 / NCN8025A is a compact and cost−effective single
smart card interface IC. It is dedicated for 1.8 V / 3.0 V / 5.0 V smart
card reader/writer applications. The card VCC supply is provided by a
built−in very low drop out and low noise LDO.
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The device is fully compatible with the ISO 7816−3, EMV 4.3,
UICC and related standards including NDS and other STB standards
(Nagravision, Irdeto...). It satisfies the requirements specifying
MARKING
DIAGRAMS
conditional access into Set−Top−Boxes (STB) or Conditional Access
Modules (CAM and CAS).
This smart card interface IC is available in a QFN−24 package
(NCN8025A) providing all of the industry−standard features usually
QFN24
MN SUFFIX
CASE 485L
NCN
8025A
ALYWG
G
required for STB smart card interface. It is also offered in a very
compact package profile, QFN−16 (NCN8025), satisfying the
requirements of cost−efficiency and space−saving requested by CAM
and SIM applications.
QFN16
NCN
MT SUFFIX
8025
1
CASE 488AK
ALYWG
G
For details regarding device implementation refer to application
note AND8003/D, available upon request (please contact your local
ON Semiconductor sales office or representative).
A = Assembly Location
L = Wafer Lot
Y = Year
Features
• Single IC Card Interface
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
• Fully Compatible with ISO 7816−3, EMV 4.3, UICC and Related
Standards Including NDS and Other STB Standards (Nagravision,
Irdeto...)
• 3 Bidirectional Buffered I/O Level Shifters (C4, C7 and C8)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
(QFN−24) − 1 Bidirectional I/O Level Shifter for the QFN−16
compact version
• 1.8 V, 3.0 V or 5.0 V $ 5 % Regulated Card Power Supply
Generation such as ICC v 70 mA
• Regulator Power Supply: VDDP = 2.7 V to 5.5 V (@ 1.8 V),
3.0 V to 5.5 V (@ 3.0 V) & 4.85 V to 5.5 V (@ 5.0 V)
• Independent Power Supply range on Controller
• Interrupt Signal INT for Card Presence and Faults
Interface such as VDD = 2.7 V to 5.5 V
• Handles Class A, B and C Smart Cards
• External Under−Voltage Lockout Threshold
Adjustment on VDD (PORADJ Pin) (Except QFN−16)
• Short Circuit Protection on all Card Pins
• Available in 2 Package Formats: QFN−24
• Support up to 27 MHz input Clock with Internal
Division Ratio 1/1, 1/2, 1/4 and 1/8 through CLKDIV1
(NCN8025A) and QFN−16 (NCN8025)
• These are Pb−Free Devices
and CLKDIV2
• ESD Protection on Card Pins up to +8 kV (Human
Body Model)
• Activation / Deactivation Sequences (ISO7816
Sequencer)
• Fault Protection Mechanisms Enabling Automatic
Device Deactivation in Case of Overload, Overheating,
Card Take−off or Power Supply Drop−out (OCP, OTP,
Typical Application
• Pay TV, Set Top Box Decoder with Conditional Access
and Pay−per−View
• Conditional Access Module (CAM / CAS)
• SIM card interface applications (UICC / USIM)
• Point Of Sales and Transaction Terminals
• Electronic Payment and Identification
UVP)
© Semiconductor Components Industries, LLC, 2016
October, 2016 − Rev. 5
1
Publication Order Number:
NCN8025/D
1 page  
NCN8025 / NCN8025A
ATTRIBUTES
Characteristics
ESD protection
Human Body Model (HBM) (Note 1)
Card Pins (card interface pins 3−11)
All Other Pins
Machine Model (MM)
Card Pins (card interface pins 3−11)
All Other Pins
Moisture sensitivity (Note 2) QFN−24 and QFN−16
Flammability Rating Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. Human Body Model (HBM), R = 1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
Values
8 kV
2 kV
400 V
150 V
Level 1
UL 94 V−0 @ 0.125 in
MAXIMUM RATINGS (Note 3)
Rating
Symbol
Value
Unit
Regulator Power Supply Voltage
Power Supply from Microcontroller Side
External Card Power Supply
VDDP
VDD
CVCC
−0.3 ≤ VDDP ≤ 5.5
−0.3 ≤ VDD ≤ 5.5
−0.3 ≤ CVCC ≤ 5.5
V
V
V
Digital Input Pins
Digital Output Pins (I/Ouc, AUX1uc, AUX2uc, INT)
Smart card Output Pins
Thermal Resistance Junction−to−Air (Note 4)
QFN−24
QFN−16
Vin
Vout
Vout
RqJA
−0.3 ≤ Vin ≤ VDD
−0.3 ≤ Vout ≤ VDD
−0.3 ≤ Vout ≤ CVCC
37
48
V
V
V
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature Range
TJ
−40 to +125
°C
Maximum Junction Temperature
TJmax
+125
°C
Storage Temperature Range
Tstg
−65 to + 150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C.
4. Exposed Pad (GND) must be connected to PCB.
www.onsemi.com
5
5 Page 
NCN8025 / NCN8025A
If controlling the clock with RSTIN is not necessary
(Normal Mode), then CMDVCC can be set LOW with
RSTIN LOW. In that case, CLK will start minimum 500 ns
after the transition on I/O (Figure 6), and to obtain an ATR,
CRST can be set High by RSTIN also about 500 ns after the
clock channel activation (Tact).
The internal activation sequence activates the different
channels according to a specific hardware built−in
sequencing internally defined but at the end the actual
activation sequencing is the responsibility of the application
software and can be redefined by the micro−controller to
comply with the different standards and the different ways
the standards manage this activation (for example light
differences exist between the EMV and the ISO7816
standards).
CMDVCC
CVCC
CIO
CCLK
ATR
RSTIN
CRST
t0 t1 t2 t4
t5
~200 ms
Figure 5. Activation Sequence − RSTIN Mode (RSTIN Starting High)
CMDVCC
CVCC
CIO
CCLK
RSTIN
CRST
ATR
t0 t1 t2 t3
t4
Tact
Figure 6. Activation Sequence − Normal Mode
www.onsemi.com
11
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet NCN8025.PDF ] | |
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