DataSheet26.com

CD4001BMS PDF даташит

Спецификация CD4001BMS изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS NOR Gate».

Детали детали

Номер произв CD4001BMS
Описание CMOS NOR Gate
Производители Intersil Corporation
логотип Intersil Corporation логотип 

9 Pages
scroll

No Preview Available !

CD4001BMS Даташит, Описание, Даташиты
CD4000BMS, CD4001BMS
CD4002BMS, CD4025BMS
November 1994
CMOS NOR Gate
Features
Pinouts
• High-Voltage Types (20V Rating)
• Propagation Delay Time = 60ns (typ.) at CL = 50pF,
VDD = 10V
• Buffered Inputs and Outputs
• Standard Symmetrical Output Characteristics
• 100% Tested for Maximum Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Device’s
Description
CD4000BMS
CD4001BMS
CD4002BMS
CD4025BMS
- Dual 3 Plus Inverter
- Quad 2 Input
- Dual 4 Input
- Triple 3 Input
CD4000BMS
TOP VIEW
NC 1
14 VDD
NC 2
13 F
A3
12 E
B4
11 D
C5
10 K = D + E + F
H=A+B+C 6
9 L=G
VSS 7
8G
NC = NO CONNECTION
CD4001BMS
TOP VIEW
A1
14 VDD
B2
13 H
J=A+B 3
12 G
K=C+D 4
11 M = G + H
C5
10 L = E + F
D6
9F
VSS 7
8E
NC = NO CONNECTION
CD4002BMS
TOP VIEW
CD4000BMS, CD4001BMS, CD4002BMS, and
CD4025BMS NOR gates provide the system designer with
direct implementation of the NOR function and supplement
the existing family of CMOS gates. All inputs and outputs are
buffered.
The CD4000BMS, CD4001BMS, CD4002BMS and the
CD4025BMS is supplied in these 14 lead outline packages:
CD4000B CD4001B CD4002B CD4025B
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1B
H3W
H4Q
H1B
H3W
H4Q
H1B
H3W
H4Q
H1B
H3W
J=A+B+C+D 1
14 VDD
A2
13 K = E + F + G + H
B3
12 H
C4
11 G
D5
10 F
NC 6
9E
VSS 7
8 NC
NC = NO CONNECTION
CD4025BMS
TOP VIEW
A1
B2
D3
14 VDD
13 G
12 H
E4
F5
K=D+E+F 6
VSS 7
11 I
10 L = G + H + I
9 J=A+B+C
8C
NC = NO CONNECTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-649
File Number 3289









No Preview Available !

CD4001BMS Даташит, Описание, Даташиты
CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS
Functional Diagrams
NC 1
NC 2
A3
B4
C5
H6
VSS 7
K=D+E+F
14 VDD
13 F
12 E
11 D
H=A+B+C
10 K
9L
L=G
CD4000BMS
8G
A 1 J=A+B
M = G + H 14 VDD
B2
13 H
J3
K=C+D
K4
12 G
11 M
C5
10 L
D6
VSS 7
L=E+F
CD4001BMS
9F
8E
J1
J=A+B+C+D
A2
14 VDD
13 K
B3
12 H
C4
11 G
D5
10 F
NC 6
VSS 7
K=E+F+G+H
9E
8 NC
CD4002BMS
A1
14 VDD
B2
D3
13 G
L=G+H+I
12 H
E4
11 I
F5
10 L
K6
K=D+E+F
VSS 7
J=A+B+C
CD4025BMS
9J
8C
7-650









No Preview Available !

CD4001BMS Даташит, Описание, Даташиты
Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 0.5 µA
2
+125oC
- 50 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 0.5 µA
Input Leakage
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
7
7
+25oC
+25oC
VOH > VOL < V
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
Input Voltage High
(Note 2)
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
Input Voltage Low
(Note 2)
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC -
4V
Input Voltage High
(Note 2)
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs
7-651










Скачать PDF:

[ CD4001BMS.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
CD4001BMQuad 2-Input NOR/NAND Buffered B Series GateNational Semiconductor
National Semiconductor
CD4001BMSCMOS NOR GateIntersil Corporation
Intersil Corporation

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск