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PDF CD40106BMS Data sheet ( Hoja de datos )

Número de pieza CD40106BMS
Descripción CMOS Hex Schmitt Triggers
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! CD40106BMS Hoja de datos, Descripción, Manual

CD40106BMS
December 1992
CMOS Hex Schmitt Triggers
Features
Pinout
• High Voltage Type (20V Rating)
• Schmitt Trigger Action with No External Components
CD40106BMS
TOP VIEW
• Hysteresis Voltage (Typ.)
- 0.9V at VDD = 5V
- 2.3V at VDD = 10V
- 3.5V at VDD = 15V
• Noise Immunity Greater than 50%
• No Limit on Input Rise and Fall Times
• Low VDD to VSS Current During Slow Input Ramp
• 100% Tested for Quiescent Current at 20V
A1
G=A 2
B3
H=B 4
C5
I=C 6
VSS 7
14 VDD
13 F
12 L = F
11 E
10 K = E
9D
8 J=D
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
Functional Diagram
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
1
A
3
B
2
G=A
4
H=B
Applications
5
C
6
I=C
• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
• Astable Multivibrators
9
D
11
E
8
J=D
10
K=E
Description
13
F
12
L=F
CD40106BMS consists of six Schmitt trigger circuits. Each
circuit functions as an inverter with Schmitt trigger action on
the input. The trigger switches at different points for positive
and negative going signals. The difference between the
positive going voltage (VP) and the negative going voltage
(VN) is defined as hysteresis voltage (VH) (see Figure 17).
The CD40106BMS is supplied in these 14 lead outline
packages:
Logic Diagram
A*
1 (3, 5, 9, 11, 13)
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
*G
2 (4, 6, 8, 10, 12)
VDD
FIGURE 1. 1 OF 6 SCHMITT TRIGGERS
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1327
File Number 3354

1 page




CD40106BMS pdf
Specifications CD40106BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 2, 4, 6, 8, 10, 12 1, 3, 5, 7, 9, 11, 13
Note 1
14
Static Burn-In 2 2, 4, 6, 8, 10, 12
Note 1
7
1, 3, 5, 9, 11,
13, 14
Dynamic Burn-
In Note 1
-
7 14 2, 4, 6, 8, 10, 12 1, 3, 5, 9, 11, 13
Irradiation
Note 2
2, 4, 6, 8, 10, 12
7
1, 3, 5, 9, 11,
13, 14
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5 5V
0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
7-1331

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