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8413S12I-100 PDF даташит

Спецификация 8413S12I-100 изготовлена ​​​​«IDT» и имеет функцию, называемую «Clock Generator».

Детали детали

Номер произв 8413S12I-100
Описание Clock Generator
Производители IDT
логотип IDT логотип 

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8413S12I-100 Даташит, Описание, Даташиты
Clock Generator for Cavium
Processors
8413S12I-100
Data Sheet
General Description
Features
The 8413S12I-100 is a PLL-based clock generator specifically
designed for Cavium Networks Octeon II processors. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express reference clocks and the clocks for
both the Gigabit Ethernet MAC and PHY. The clock generator offers
ultra low-jitter, low-skew clock outputs, and edge rates that easily
meet the input requirements for the CN63XX and CN68XX series of
processors. The output frequencies are generated from a 25MHz
external input source or an external 25MHz parallel resonant crystal.
The industrial temperature range of the 8413S12I-100 supports
telecommunication, networking, and storage requirements.
Applications
Systems using Cavium Processors
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
Ten 100MHz clocks for PCI Express, HCSL interface levels
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15output impedance
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Pin Assignment
GND
nc
nc
nc
nc
nc
nc
nc
nc
nc
VDDA
nc
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1 54
2 53
3 52
4 51
5 50
6 8XXXXXX
7
49
48
8 47
9
10
8413S12I-100
46
45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
nc
VDD
IREF
OE_D
nQD1
QD1
nQD0
QD0
VDDO_D
VDDO_C
nQC1
QC1
nQC0
QC0
OE_C
VDD
GND
nc
©2016 Integrated Device Technology, Inc.
72-pin, 10mm x 10mm LQFP Package
1 October 4, 2016









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8413S12I-100 Даташит, Описание, Даташиты
Block Diagram
8413S12I-100 Data Sheet
nMR
Pullup
PLL_SEL
REF_SEL
CLK
nCLK
XTAL_IN
XTAL_OUT
IREF
Pullup
Pullup
Pulldown
Pullup/Pulldown
OSC
0
1
VCO
100MHz
100MHz
100MHz
100MHz
0
1
100MHz
50MHz
125MHz
OE_REF
OTE: OE_A, OE_B, OE_C, OE_D, OE_E, OE_G, OE_REF have internal pull-up resistors.
OE_A
QA0
nQA0
QA1
nQA1
OE_B
QB0
nQB0
QB1
nQB1
OE_C
QC0
nQC0
QC1
nQC1
OE_D
QD0
nQD0
QD1
nQD1
OE_E
QE0
nQE0
QE1
nQE1
QF
OE_G
QG
QREF0
QREF1
©2016 Integrated Device Technology, Inc.
2
October 4, 2016









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8413S12I-100 Даташит, Описание, Даташиты
8413S12I-100 Data Sheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 18, 38
11
2, 3, 4, 5, 6,
7, 8, 9, 10,
12, 13, 16,
19, 36, 37,
54, 55, 72
14,
15
17
20, 39, 53
21
Name
GND
VDDA
nc
XTAL_IN,
XTAL_OUT
REF_SEL
VDD
PLL_SEL
Type
Power
Power
Unused
Input
Input
Power
Input
Pullup
Pullup
Description
Power supply ground.
Analog supply pin.
No connect.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Input source control pin. See Table 3B. LVCMOS/LVTTL interface levels.
Core supply pins.
PLL bypass control pin. See Table 3A. LVCMOS/LVTTL interface levels.
22 CLK Input Pulldown Non-inverting differential clock input.
23
24
25
26, 27
28, 29
30
31, 32
33, 34
35
40
nCLK
OE_A
VDDO_A
QA0, nQA0
QA1, nQA1
OE_B
QB0, nQB0
QB1, nQB1
VDDO_B
OE_C
Input
Input
Power
Output
Output
Input
Output
Output
Power
Input
Pullup/
Pulldown
Pullup
Pullup
Pullup
Inverting differential clock input. Internal resistor bias to VDD/2.
Active HIGH output enable for Bank A outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Bank A (HCSL) output supply pin. 3.3 V supply.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Active HIGH output enable for Bank B outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank B (HCSL) output supply pin. 3.3V supply.
Active HIGH output enable for Bank C outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
41, 42
QC0, nQC0 Output
Differential output pair. HCSL interface levels.
43, 44
QC1, nQC1 Output
Differential output pair. HCSL interface levels.
45
VDDO_C
Power
46
VDDO_D
Power
Bank C (HCSL) output supply pin. 3.3V supply.
Bank D (HCSL) output and HCSL reference circuit supply pin. Must be connected
to 3.3V to use any of the HCSL outputs.
47, 48
49, 50
51
52
56
57, 58
QD0, nQD0
QD1, nQD1
OE_D
Output
Output
Input
IREF
VDDO_E
QE0, nQE0
Input
Power
Output
Pullup
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Active HIGH output enable for Bank D outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
External fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode Q[Ax:Ex], nQ[Ax:EX] outputs.
Bank E (HCSL) output supply pin. 3.3V supply.
Differential output pair. HCSL interface levels.
59, 60
61
QE1, nQE1
OE_E
Output
Input
Pullup
Differential output pair. HCSL interface levels.
Active HIGH output enable for Bank E outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
©2016 Integrated Device Technology, Inc.
3
October 4, 2016










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