9DML04 PDF даташит
Спецификация 9DML04 изготовлена «IDT» и имеет функцию, называемую «2:4 3.3V PCIe Clock Mux». |
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Детали детали
Номер произв | 9DML04 |
Описание | 2:4 3.3V PCIe Clock Mux |
Производители | IDT |
логотип |
13 Pages
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2:4 3.3V PCIe Clock Mux
9DML04
Description
The 9DML04 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DML04 supports PCIe
Gen1-4 Common Clocked (CC), Separate Reference no
Spread (SRnS), and Separate Reference Independent
Spread (SRIS) architectures. The part provides a choice of
asynchronous and glitch-free switching modes, and offers a
choice of integrated output terminations providing direct
connection to 85 or 100 transmission lines. The
9DML04P1 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
Servers, ATCA, ATE, Master/Slave applications
Output Features
• 4 – 1~200 MHz Low-Power HCSL (LP-HCSL) DIF pairs
• 9DML0441 default ZOUT = 100
• 9DML0451 default ZOUT = 85
• 9DML04P1 factory programmable defaults
Key Specifications
• PCIe Gen1-2-3-4 CC compliant
• PCIe Gen2-3 SRIS compliant
• DIF additive cycle-to-cycle jitter <1ps
• DIF output-to-output skew <50ps
• Additive phase jitter is <0.1ps rms for PCIe
• Additive phase jitter 160fs rms typ. @156.25M (1.5M to
10M)
Block Diagram
^OE(3:0)#
4
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
DATASHEET
Features/Benefits
• Direct connection to 100 (xx41) or 85 (xx51)
transmission lines; saves 16 resistors compared to
standard PCIe devices
• 76mW typical power consumption; eliminates thermal
concerns
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• Customer defined power up default can be factory
programmed into P1 device; allows exact optimization to
customer requirements:
• control input polarity
• control input pull up/downs
• slew rate for each output
• differential output amplitude
• output impedance for each output
• OE# pins; support DIF power management
• HCSL-compatible differential inputs; can be driven by
common clock source
• Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
DIF3
A DIF2
B DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DML04 REVISION A 06/06/16
1 ©2015 Integrated Device Technology, Inc.
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9DML04 DATASHEET
Pin Configuration
DIF_INA 1
DIF_INA# 2
VDDR3.3 3
VDDR3.3 4
DIF_INB 5
DIF_INB# 6
24 23 22 21 20 19
9DML04xx
Connect ePad
to GND
18 DIF2#
17 DIF2
16 VDD3.3
15 GND
14 DIF1#
13 DIF1
7 8 9 10 11 12
24 VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
Power Management Table
OEx# Pin
0
1
DIF_IN
Running
Running
DIFx
True O/P Comp. O/P
Running
Running
Low Low
Power Connections
Pin Number
VDD
GND
3 24
47
16 15
Description
Input A receiver analog
Input B receiver analog
DIF outputs
2:4 3.3V PCIE CLOCK MUX
2
REVISION A 06/06/16
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Pin Descriptions
Pin# Pin Name
1 DIF_INA
2 DIF_INA#
3 VDDR3.3
4 VDDR3.3
5 DIF_INB
6 DIF_INB#
7 GNDR
8 vSW_MODE
9 ^OE0#
10 DIF0
11 DIF0#
12 ^OE1#
13 DIF1
14 DIF1#
15 GND
16 VDD3.3
17 DIF2
18 DIF2#
19 ^OE2#
20 DIF3
21 DIF3#
22 ^OE3#
23 ^SEL_A_B#
24 GNDR
25 EPAD
9DML04 DATASHEET
Type
IN
IN
PWR
PWR
IN
IN
GND
IN
IN
OUT
OUT
IN
OUT
OUT
GND
PWR
OUT
OUT
IN
OUT
OUT
IN
IN
GND
GND
Pin Description
HCSL Differential True input
HCSL Differential Complement Input
3.3V power for differential input clock (receiver). This VDD should be treated
as an Analog power rail and filtered appropriately.
3.3V power for differential input clock (receiver). This VDD should be treated
as an Analog power rail and filtered appropriately.
HCSL Differential True input
HCSL Differential Complement Input
Analog Ground pin for the differential input (receiver)
Switch Mode. This pin selects either asynchronous or glitch-free switching of
the mux. Use asynchronous mode if 0 or 1 of the input clocks is running.
Use glitch-free mode if both input clocks are running. This pin has an internal
pull down resistor of ~120kohms.
0 = asynchronous mode
1 = glitch-free mode
Active low input for enabling DIF pair 0. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
Input to select differential input clock A or differential input clock B. This
input has an internal pull-up resistor.
0 = Input B selected, 1 = Input A selected.
Analog Ground pin for the differential input (receiver)
Connect to Ground.
REVISION A 06/06/16
3 2:4 3.3V PCIE CLOCK MUX
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Номер в каталоге | Описание | Производители |
9DML04 | 2:4 3.3V PCIe Clock Mux | IDT |
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