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9DMU0141 PDF даташит

Спецификация 9DMU0141 изготовлена ​​​​«IDT» и имеет функцию, называемую «2:1 1.5V PCIe Gen1-2-3 Clock Mux».

Детали детали

Номер произв 9DMU0141
Описание 2:1 1.5V PCIe Gen1-2-3 Clock Mux
Производители IDT
логотип IDT логотип 

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9DMU0141 Даташит, Описание, Даташиты
2:1 1.5V PCIe Gen1-2-3 Clock Mux
w/Zo=100ohms
9DMU0141
DATASHEET
General Description
The 9DMU0141 is a member of IDT's SOC-Friendly 1.5V
Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has
integrated output terminations providing Zo=100ohms for
direct connection to 100ohm transmission lines. The output
has an OE# pin for optimal system control and power
management. The part provides asynchronous or glitch-free
switching modes.
Recommended Application
2:1 1.5V PCIe Gen1-2-3 Clock Mux
Output Features
1 – Low-Power (LP) HCSL DIF pair w/Zo=100
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
125MHz additive phase jitter 535fs rms typical (12kHz to
20MHz)
Features/Benefits
LP-HCSL output w/integrated terminations; saves 4
resistors compared to standard HCSL output
1.5V operation; 11mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 167MHz operating frequency
Space saving 16-pin 3x3mm VFQFPN; minimal board
space
Block Diagram
^OE0#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
A
DIF0
B
9DMU0141 REVISION A 09/30/14
1
©2014 Integrated Device Technology, Inc.









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9DMU0141 Даташит, Описание, Даташиты
9DMU0141 DATASHEET
Pin Configuration
GNDR 1
VDDR1.5 2
VDDR1.5 3
GNDR 4
16 15 14 13
12 VDD1.5
11 GND
9DMU0141
10 DIF0#
9 DIF0
5678
16-pin VFQFPN, 3x3 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
Note: Paddle may be connected to ground for thermal
purposes. It is not required electrically.
Power Management Table
Power Connections
OEx# Pin
0
1
DIF_IN
Running
Running
DIFx
True O/P Comp. O/P
Running
Running
Low Low
Pin Number
VDD
GND
21
34
12 11
Description
Input A receiver analog
Input B receiver analog
DIF outputs
Pin Descriptions
Note: Pins 2 and 3 should be decoupled separately to
pins 1 and 4 respectively.
Pin# Pin Name
1 GNDR
2 VDDR1.5
3 VDDR1.5
4 GNDR
5 DIF_INB
6 DIF_INB#
7 vSW_MODE
8 ^OE0#
9 DIF0
10 DIF0#
11 GND
12 VDD1.5
13 NC
14 ^SEL_A_B#
15 DIF_INA
16 DIF_INA#
Type
GND
PWR
PWR
GND
IN
IN
IN
IN
OUT
OUT
GND
PWR
N/A
IN
IN
IN
Pin Description
Analog Ground pin for the differential input (receiver)
1.5V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
1.5V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
Analog Ground pin for the differential input (receiver)
HCSL Differential True input
HCSL Differential Complement Input
Switch Mode. This pin selects either asynchronous or glitch-free switching of the mux. Use
asynchronous mode if 0 or 1 of the input clocks is running. Use glitch-free mode if both input
clocks are running. This pin has an internal pull down resistor of ~120kohms.
0 = asynchronous mode
1 = glitch-free mode
Active low input for enabling DIF pair 0. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply, nominally 1.5V
No Connection.
Input to select differential input clock A or differential input clock B. This input has an internal
pull-up resistor.
0 = Input B selected, 1 = Input A selected.
HCSL Differential True input
HCSL Differential Complement Input
2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS
2
REVISION A 09/30/14









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9DMU0141 Даташит, Описание, Даташиты
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100ohm
Rs
Device
2pF 2pF
Driving LVDS
Driving LVDS
Rs
Device
Rs
Cc
Cc
3.3V
R7a
Zo
R8a
R7b
R8b
LVDS Clock
input
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
9DMU0141 DATASHEET
REVISION A 09/30/14
3 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS










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