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9DMU0441 PDF даташит

Спецификация 9DMU0441 изготовлена ​​​​«IDT» и имеет функцию, называемую «2:4 1.5V PCIe Gen1-2-3 Clock Mux».

Детали детали

Номер произв 9DMU0441
Описание 2:4 1.5V PCIe Gen1-2-3 Clock Mux
Производители IDT
логотип IDT логотип 

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9DMU0441 Даташит, Описание, Даташиты
2:4 1.5V PCIe Gen1-2-3 Clock Mux
w/Zo=100ohms
9DMU0441
DATASHEET
General Description
The 9DMU0441 is a member of IDT's SOC-Friendly 1.5V
Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has
integrated output terminations providing Zo=100ohms for
direct connection to 100ohm transmission lines. Each of the 4
outputs has its own dedicated OE# pin for optimal system
control and power management. The part provides
asynchronous and glitch-free switching modes.
Recommended Application
2:4 PCIe Gen1-2-3 clock multiplexer
Output Features
4 – Low-Power (LP) HCSL DIF pairs w/Zo=100
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Additive phase jitter @ 125MHz: 535fs rms typical (12kHz
to 20MHz)
DIF output-to-output skew <50ps
Features/Benefits
LP-HCSL outputs w/integrated terminations; saves 16
resistors compared to standard HCSL outputs
1.5V operation; 26mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 167MHz operating frequency
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
4
,
A
B
DIF3
DIF2
DIF1
DIF0
9DMU0441 REVISION A 09/24/14
1
©2014 Integrated Device Technology, Inc.









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9DMU0441 Даташит, Описание, Даташиты
9DMU0441 DATASHEET
Pin Configuration
DIF_INA 1
DIF_INA# 2
VDDR1.5 3
VDDR1.5 4
DIF_INB 5
DIF_INB# 6
24 23 22 21 20 19
18 DIF2#
9DMU0441
Connect ePad
to GND
17 DIF2
16 VDD1.5
15 GND
14 DIF1#
13 DIF1
7 8 9 10 11 12
24 VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
Power Management Table
OEx# Pin
0
1
DIF_IN
Running
Running
DIFx
True O/P Comp. O/P
Running
Running
Low Low
Pin Descriptions
Power Connections
Pin Number
VDD
GND
3 24
47
16 15
Description
Input A receiver analog
Input B receiver analog
DIF outputs
Pin# Pin Name
1 DIF_INA
2 DIF_INA#
3 VDDR1.5
4 VDDR1.5
5 DIF_INB
6 DIF_INB#
7 GNDR
8 vSW_MODE
9 ^OE0#
10 DIF0
11 DIF0#
12 ^OE1#
13 DIF1
14 DIF1#
15 GND
Type
IN
IN
PWR
PWR
IN
IN
GND
IN
IN
OUT
OUT
IN
OUT
OUT
GND
Pin Description
HCSL Differential True input
HCSL Differential Complement Input
1.5V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
1.5V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
HCSL Differential True input
HCSL Differential Complement Input
Analog Ground pin for the differential input (receiver)
Switch Mode. This pin selects either asynchronous or glitch-free switching of the mux. Use
asynchronous mode if 0 or 1 of the input clocks is running. Use glitch-free mode if both input
clocks are running. This pin has an internal pull down resistor of ~120kohms.
0 = asynchronous mode
1 = glitch-free mode
Active low input for enabling DIF pair 0. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Ground pin.
2:4 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS
2
REVISION A 09/24/14









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9DMU0441 Даташит, Описание, Даташиты
9DMU0441 DATASHEET
Pin Descriptions (cont.)
Pin# Pin Name
16 VDD1.5
17 DIF2
18 DIF2#
19 ^OE2#
20 DIF3
21 DIF3#
22 ^OE3#
23 ^SEL_A_B#
24 GNDR
25 EPAD
Type
PWR
OUT
OUT
IN
OUT
OUT
IN
IN
GND
GND
Pin Description
Power supply, nominally 1.5V
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Input to select differential input clock A or differential input clock B. This input has an internal
pull-up resistor.
0 = Input B selected, 1 = Input A selected.
Analog Ground pin for the differential input (receiver)
Connect to Ground.
REVISION A 09/24/14
3 2:4 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS










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