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Número de pieza | 9ZML1232 | |
Descripción | 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX | |
Fabricantes | IDT | |
Logotipo | ||
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No Preview Available ! 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
DATASHEET
9ZML1232
General Description
The 9ZML1232 is a 2-input/12-output differential mux for
use in servers. It meets the demanding DB1200ZL
performance specifications and utilizes Low-Power
HCSL-compatible outputs to reduce power consumption
and termination components. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI
applications.
Recommended Application
Clock Mux for Romley, Grantley and Purley Servers
Output Features
• 12 - Low-Power (LP) HCSL Output Pairs
Block Diagram
y
Features/Benefits
• Fixed feedback path; 0ps input-to-output delay
• 9 Selectable SMBus addresses; multiple devices can
share same SMBus segment
• Separate VDDIO for outputs; allows maximum power
savings
• PLL or bypass mode; PLL can dejitter incoming clock
• Hardware or Software-selectable PLL BW; minimizes
jitter peaking in downstream PLL's
• Spread spectrum compatible; tracks spreading input
clock for EMI reduction
• SMBus Interface; unused outputs can be disabled
• Differential outputs are Low/Low in power down;
maximum power savings
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew <65 ps
• Input-to-output delay: Fixed at 0 ps
• Input-to-output delay variation <50ps
• Phase jitter: PCIe Gen3 <1ps rms
• Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms
y
OE(11:0)#
DIF_INB
DIF_INB#
DIF_INA
DIF_INA#
HIBW_BYPM_LOBW#
SEL_A_B#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
FBOUT_NC
DIF(11:0)
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2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZML1232. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDDA, R
3.3V Logic Supply Voltage VDD
I/O Supply Voltage
VDDIO
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0.5
-65
2000
TYP
MAX
4.6
4.6
4.6
VDD+0.5V
5.5V
150
125
UNITS NOTES
V 1,2
V 1,2
V 1,2
V1
V1
V1
°C 1
°C 1
V1
Electrical Characteristics–DIF_IN Clock Input Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
Input Swing - DIF_IN
VCROSS
VSWING
Cross Over Voltage
Differential value
150 900 mV 1
300 mV 1
Input Slew Rate - DIF_IN dv/dt
Measured differentially
0.4
8 V/ns 1,2
Input Leakage Current
Input Duty Cycle
IIN
dtin
VIN = VDD , VIN = GND
Measurement from differential wavefrom
-5
45
5 uA
55 % 1
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
0
125 ps 1
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2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
DIF Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, route as non-coupled 50ohm trace
0.5 max
L2 length, route as non-coupled 50ohm trace
0.2 max
L3 length, route as non-coupled 50ohm trace
0.2 max
Rs (100 ohm differential traces)
33
Rs (85 ohm differential traces)
27
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max
Unit Figure
inch 1
inch 1
inch 1
ohm 1
ohm 1
inch 1
inch 1
inch 2
inch 2
Figure 1: Down Device Routing
LP-HCSL
Output
L1
Rs
L1'
Rs
L2
L2'
L4
L4'
PCI Express
Down Device
REF_CLK Input
Figure 2: PCI Express Connector Routing
LP-HCSL
Output
L1 L2
Rs
L1' L2'
Rs
L4
L4'
PCI Express
Add-in Board
REF_CLK Input
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11 Page |
Páginas | Total 19 Páginas | |
PDF Descargar | [ Datasheet 9ZML1232.PDF ] |
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