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9ZX21200 PDF даташит

Спецификация 9ZX21200 изготовлена ​​​​«IDT» и имеет функцию, называемую «12-OUTPUT DIFFERENTIAL Z-BUFFER».

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Номер произв 9ZX21200
Описание 12-OUTPUT DIFFERENTIAL Z-BUFFER
Производители IDT
логотип IDT логотип 

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9ZX21200 Даташит, Описание, Даташиты
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
DATASHEET
9ZX21200
Description
The 9ZX21200 is a small-footprint 12-output differential
buffer that meets all the performance requirements of the
Intel DB1200Z specification. The 9ZX21200 is backwards
compatible to PCIe Gen1 and Gen2 applications. A fixed,
internal feedback path maintains low drift for critical QPI
applications. In bypass mode, the 9ZX21200 can provide
outputs up to 150MHz.
Recommended Application
12-output PCIe Gen3/ QPI differential buffer for Romley and
newer platforms
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew < 65 ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter < 1.0ps RMS
QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
Features/Benefits
Space-saving 56-pin package
Fixed feedback path for 0ps input-to-output delay
9 Selectable SMBus Addresses; Mulitple devices can
share the same SMBus Segment
4 OE# pins; Hardware control of four outputs
PLL or bypass mode; PLL can dejitter incoming clock
100MHz or 133MHz PLL mode operation; supports PCIe
and QPI applications
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
Software control of PLL Bandwidth and Bypass
Settings/PLL can dejitter incoming clock (B Rev only)
Output Features
12 - 0.7V differential HCSL output pairs
Block Diagram
OE(8,6,4,2)#
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
IREF
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
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9ZX21200 Даташит, Описание, Даташиты
9ZX21200
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
Pin Configuration
GNDA 1
IREF 2
100M_133M# 3
HIBW_BYPM_LOBW 4
CKPWRGD_PD# 5
GND 6
VDDR 7
DIF_IN 8
DIF_IN# 9
SMB_A0_tri 10
SMBDAT 11
SMBCLK 12
SMB_A1_tri 13
DFB_OUT# 14
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42 GND
41 DIF_7#
40 DIF_7
39 vOE6#
38 DIF_6#
37 DIF_6
9ZX21200
36 GND
35 VDD
34 DIF_5#
33 DIF_5
32 vOE4#
31 DIF_4#
30 DIF_4
29 GND
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Notes: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldown.
Even though the feedback path is fixed, the DFB_OUT
pair still needs a termination network for the part to
function.
Power Management Table
CKP WR GD_ PD#
0
1
DIF_I N/
D IF_IN#
X
Running
SM Bus
EN bit
X
0
1
DIF(11:0 )/
D IF(1 1:0)#
Low/L ow
Low/L ow
Runn ing
PLL STATE
IF NOT IN
BYPASS
MODE
OFF
ON
ON
MLF Power Connections
Pin Number
VDD
56
7
21,35,50
VDD
22,28,43,49
GND
1
6
20,29,36,42,
51
Description
Analog PLL
Analog Input
DIF clocks
Functionality at Power-up (PLL mode)
100M _133 M#
1
0
DIF_IN
MHz
1 00.00
1 33.33
DIF(11:0)
DIF_I N
DIF_I N
PLL Operating Mode Readback Table
HiBW _By pM_LoBW #
Low (Low BW)
Mid (Bypass)
High (High BW)
Byte0, bit 7
0
0
1
Byte 0, bit 6
0
1
1
PLL Operating Mode Table
HiBW _By pM_LoBW #
MODE
Low PLL Lo BW
Mid Bypass
H igh
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
Tri-Level Input Thresholds
Le vel
Low
Mid
H igh
V olta ge
<0. 8V
1.2< Vi n<1 .8V
Vin > 2.2V
9ZX21200 SMBus Addressing
Pi n
S MB_A 1_tri
0
0
0
M
M
M
1
1
1
SMB_A0_tri SMBus Address
0 D8
M DA
1 DE
0 C2
M C4
1 C6
0 CA
M CC
1 CE
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
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9ZX21200 Даташит, Описание, Даташиты
9ZX21200
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
Pin Descriptions
PIN #
PIN NAME
1 GNDA
2 IR EF
3 100M_133M#
4 HIBW_BYPM_LOBW#
5 CKPWRGD_PD#
6 GND
7 VDDR
8 DIF_IN
9 DIF_IN#
10 SMB_A0_tri
11 SMBDAT
12 SMBCLK
13 SMB_A1_tri
14 DFB_OUT#
15 DFB_OUT
16 DIF_0
17 DIF_0#
18 DIF_1
19 DIF_1#
20 GND
21 VDD
22 VDD
23 DIF_2
24 DIF_2#
25 vOE2#
26 DIF_3
27 DIF_3#
28 VDD
29 GND
30 DIF_4
31 DIF_4#
32 vOE4#
33 DIF_5
34 DIF_5#
35 VDD
36 GND
37 DIF_6
38 DIF_6#
39 vOE6#
40 DIF_7
41 DIF_7#
42 GND
43 VDD
44 DIF_8
45 DIF_8#
46 vOE8#
47 DIF_9
48 DIF_9#
49 VDD
50 VDD
51 GND
52 DIF_10
53 DIF_10#
54 DIF_11
55 DIF_11#
56 VDDA
TYPE
DES CRIP TI ON
PWR Ground pin for the PLL core.
This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision
OUT resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances
require different values. See data sheet.
IN
3.3V Input to select operating frequency
See Functionality Table for Definition
IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for D etails.
IN
N otifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
subsequent assertions. Low enters Power Down Mode.
PWR Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
PWR filtered appropriately.
IN 0.7 V Differential TRUE input
IN 0.7 V Differential Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9
IN SMBus Addresses.
I/O D ata pin of SMBUS circuitry, 5V tolerant
IN
IN
OUT
OUT
OUT
C lock pin of SMBU S circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9
SMBus Addresses.
C omplementary half of differential feedback output, provides feedback signal to the PLL for synchronization
w ith input clock to eliminate phase error.
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input
clock to eliminate phase error.
0.7V differential true clock output
OUT 0.7V differential Complementary clock output
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Ground pin.
PWR Power supply, nominal 3.3V
PWR Power supply, nominal 3.3V
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
IN Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Power supply, nominal 3.3V
PWR Ground pin.
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
IN
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Power supply, nominal 3.3V
PWR Ground pin.
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
Active low input for enabling DIF pair 6.
IN 1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Ground pin.
PWR Power supply, nominal 3.3V
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
Active low input for enabling DIF pair 8.
IN 1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Power supply, nominal 3.3V
PWR Power supply, nominal 3.3V
PWR Ground pin.
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR 3.3V power for the PLL core.
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
3
9ZX21200
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