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9ZXL0651 PDF даташит

Спецификация 9ZXL0651 изготовлена ​​​​«IDT» и имеет функцию, называемую «6-OUTPUT LOW-POWER HCSL BUFFER».

Детали детали

Номер произв 9ZXL0651
Описание 6-OUTPUT LOW-POWER HCSL BUFFER
Производители IDT
логотип IDT логотип 

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9ZXL0651 Даташит, Описание, Даташиты
6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
DATASHEET
9ZXL0651
General Description
The 9ZXL0651 is a low-power 6-output differential buffer
that meets all the performance requirements of the Intel
DB1200Z specification. It consumes 50% less power than
standard HCSL devices and has internal terminations to
allow direct connection to 85 ohm transmission lines. The
9ZXL0651 is backwards compatible to PCIe Gen1 and
Gen2 and QPI 6.4GT/s specifications. A fixed, internal
feedback path maintains low drift for critical QPI
applications.
Recommended Application
6-Output Low-Power HCSL Buffer for PCIe Gen1-2-3 and
QPI
Output Features
6 - 0.7V low-power HCSL (LP-HCSL) output pairs
w/integrated terminations
Block Diagram
Features/Benefits
Low-Power-HCSL outputs w/Zo = 85; save power and
board space - no termination resistors required. Ideal for
blade servers.
Space-saving 40-pin VFQFPN package
Fixed feedback path for 0ps input-to-output delay
6 OE# pins; Hardware control of each output
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <65 ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter <1.0ps RMS
QPI 9.6GT/s 12UI phase jitter <0.2ps RMS
OE(5:0)#
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
CKPWRGD/PD#
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(5:0)
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
1
9ZXL0651
REV C 040115









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9ZXL0651 Даташит, Описание, Даташиты
9ZXL0651
6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
Pin Configuration
40 39 38 37 36 35 34 33 32 31
VDDA 1
9ZXL0651
30 NC
^vHIBW_BYPM_LOBW# 2
29 VDD
CKPWRGD_PD# 3
28 vOE3#
GND 4
27 DIF_3#
VDDR 5
DIF_IN 6
EPAD is GND
26 DIF_3
25 VDD
DIF_IN# 7
24 DIF_2#
SMBDAT 8
23 DIF_2
SMBCLK 9
22 vOE2#
DFB_OUT_NC# 10
21 VDD
11 12 13 14 15 16 17 18 19 20
40-VFQFPN
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Dow n Resistor
^v prefix indicates Interal Pull-Up/Dow n Resistor (biased to
VDD/2)
5mm x 5mm 0.4mm pin pitch
Pin 1
Power Management Table
CKPWRGD_PD#
0
1
DIF_IN/
DIF_IN#
X
Running
SMBus
EN bit
X
0
1
DIF(5:0)/
DIF(5:0)#
Low/Low
Low/Low
Running
PLL STATE
IF NOT IN
BYPASS
MODE
OFF
ON
ON
PLL Operating Mode
HiBW_BypM_LoBW#
Low
Mid
High
MODE
PLL Lo BW
Bypass
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
Power Connections
Pin Number
VDD
GND
1 41
54
12,16,20,24,27
,31,32,36,40
41
Description
Analog PLL
Analog Input
DIF clocks
PLL Operating Mode Readback Table
HiBW_BypM_LoBW#
Low (Low BW)
Mid (Bypass)
High (High BW)
Byte0, bit 7
0
0
1
Byte 0, bit 6
0
1
1
Tri-level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
9ZXL0651 SMBus Address
1101100 + Read/Write bit
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
2
9ZXL0651
REV C 040115









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9ZXL0651 Даташит, Описание, Даташиты
9ZXL0651
6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
Pin Descriptions
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1 VDDA
PWR 3.3V power for the PLL core.
2 ^vHIBW_BYPM_LOBW# LATCHE Trilevel input to select High BW, Bypass or Low BW mode.
D IN See PLL Operating Mode Table for Details.
3 CKPWRGD_PD#
Trays 3.3V Input notifies device to sample latched inputs and start up on first high assertion, or
exit Power Down Mode on subsequent assertions. Low enters Power Down Mode.
4 GND
GND Ground pin.
5 VDDR
PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
6 DIF_IN
IN 0.7 V Differential True input
7 DIF_IN#
IN 0.7 V Differential Complementary Input
8 SMBDAT
I/O Data pin of SMBUS circuitry, 5V tolerant
9 SMBCLK
IN Clock pin of SMBUS circuitry, 5V tolerant
Complementary half of differential feedback output, provides feedback signal to the PLL
10 DFB_OUT_NC#
OUT for synchronization with input clock to eliminate phase error. This pin should NOT be
connected on the circuit board, the feedback is internal to the package.
True half of differential feedback output, provides feedback signal to the PLL for
11 DFB_OUT_NC
OUT synchronization with the input clock to eliminate phase error. This pin should NOT be
connected on the circuit board, the feedback is internal to the package.
12 VDD
PWR Power supply, nominal 3.3V
13 vOE0#
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
14 DIF_0
OUT 0.7V differential true clock output
15 DIF_0#
OUT 0.7V differential Complementary clock output
16 VDD
PWR Power supply, nominal 3.3V
17 DIF_1
OUT 0.7V differential true clock output
18 DIF_1#
OUT 0.7V differential Complementary clock output
19 vOE1#
IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
20 VDD
PWR Power supply, nominal 3.3V
21 VDD
PWR Power supply, nominal 3.3V
22 vOE2#
IN Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
23 DIF_2
OUT 0.7V differential true clock output
24 DIF_2#
OUT 0.7V differential Complementary clock output
25 VDD
PWR Power supply, nominal 3.3V
26 DIF_3
OUT 0.7V differential true clock output
27 DIF_3#
OUT 0.7V differential Complementary clock output
28 vOE3#
IN Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
29 VDD
PWR Power supply, nominal 3.3V
30 NC
N/A No Connection.
31 VDD
PWR Power supply, nominal 3.3V
32 vOE4#
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
33 DIF_4
OUT 0.7V differential true clock output
34 DIF_4#
OUT 0.7V differential Complementary clock output
35 VDD
PWR Power supply, nominal 3.3V
36 DIF_5
OUT 0.7V differential true clock output
37 DIF_5#
OUT 0.7V differential Complementary clock output
38 vOE5#
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
39 VDD
PWR Power supply, nominal 3.3V
40 NC
N/A No Connection.
41 EPAD
GND Ground Pad.
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
3
9ZXL0651
REV C 040115










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