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9ZX21901B PDF даташит

Спецификация 9ZX21901B изготовлена ​​​​«IDT» и имеет функцию, называемую «19-Output Differential Zbuffer».

Детали детали

Номер произв 9ZX21901B
Описание 19-Output Differential Zbuffer
Производители IDT
логотип IDT логотип 

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9ZX21901B Даташит, Описание, Даташиты
DATASHEET
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
9ZX21901B
Description
Features/Benefits
The 9ZX21901 is a version of the Intel DB1900Z Differential Buffer
with an ajdustable external feedback path allowing the user to
eliminate trace delays from their design. It is suitable for PCIe Gen3
or QPI applications. The part is backwards compatible to PCIe
Gen1 and Gen2. The device maintains low drift for critical QPI
applications. In bypass mode, the IDT9ZX21901 can provide outputs
up to 400MHz.
Recommended Application
19 output PCIe Gen3/QPI buffer with adjustable feedback for Romley
platforms
Output Features
• 19 - 0.7V current mode differential HCSL output pairs
External feedback path; Adjustable input-to-output delay
9 Selectable SMBus addresses/ Multiple devices can
share same SMBus segment
8 dedicated OE# pins/ hardware control of outputs
PLL or bypass mode/ PLL can dejitter incoming clock
Selectable PLL BW/ minimizes jitter peaking in
downstream PLL's
Spread spectrum compatible/tracks spreading input clock
for EMI reduction
SMBus Interface/ unused outputs can be disabled
100MHz & 133.33MHz PLL mode/ Legacy QPI support
Undriven differential outputs in Power Down mode for
maximum power savings
Key Specifications
• Cycle-to-cycle jitter: < 50ps
• Output-to-output skew: <65ps
• Input-to-output delay: User adjustable
• Input-to-output delay variation: <50ps
• Phase jitter: PCIe Gen3 < 1ps rms
Functional Block Diagram
• Phase jitter: QPI 9.6GB/s < 0.2ps rms
OE(5_12)#
8
DIF_IN
DIF_IN#
DFB_IN
DFB_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT
DIF(18:0)
IREF
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
1
1586P - 11/19/15









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9ZX21901B Даташит, Описание, Даташиты
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA 1
54 OE11#
GNDA 2
53 DIF_11#
IREF 3
52 DIF_11
100M_133M# 4
51 OE10#
HIBW_BYPM_LOBW# 5
50 DIF_10#
CKPWRGD_PD# 6
49 DIF_10
GND 7
48 OE9#
VDDR 8
47 DIF_9#
DIF_IN 9
DIF_IN# 10
9ZX21901B
46 DIF_9
45 VDD
SMB_A0_tri 11
44 GND
SMBDAT 12
43 OE8#
SMBCLK 13
42 DIF_8#
SMB_A1_tri 14
41 DIF_8
DFB_IN 15
40 OE7#
DFB_IN# 16
39 DIF_7#
DFB_OUT# 17
38 DIF_7
DFB_OUT 18
37 OE6#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72-pin MLF
PLL Operating Mode Readback Table
HiBW_BypM_LoBW# Byte0, bit 7
Low (Low BW)
0
Mid (Bypass)
0
High (High BW)
1
Byte 0, bit 6
0
1
1
Functionality at Power Up (PLL Mode)
100M_133M#
DIF_IN
(MHz)
1 100.00
0 133.33
DIF
(MHz)
DIF_IN
DIF_IN
PLL Operating Mode
HiBW_BypM_LoBW#
MODE
Low PLL Lo BW
Mid
High
Bypass
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
Tri-level Input Thresholds
Level
Voltage
Low <0.8V
Mid 1.2<Vin<1.8V
High
Vin > 2.2V
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Power Connections
Pin Number
VDD
1
8
21, 31, 45,
58, 68
GND
2
7
26, 44, 63
Description
Analog PLL
Analog Input
DIF clocks
9ZX21901 SMBus Addressing
Pin SMBus Address
SMB_A1_tri SMB_A0_tri (Rd/Wrt bit = 0)
00
D8
0M
DA
01
DE
M0
C2
MM
C4
M1
C6
10
CA
1M
CC
11
CE
1586P - 11/19/15
2









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9ZX21901B Даташит, Описание, Даташиты
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Pin Description
PIN #
PIN NAME
1 VDDA
2 GNDA
3 IREF
4 100M_133M#
5 HIBW_BYPM_LOBW#
6 CKPWRGD_PD#
7 GND
8 VDDR
9 DIF_IN
10 DIF_IN#
11 SMB_A0_tri
12 SMBDAT
13 SMBCLK
14 SMB_A1_tri
15 DFB_IN
16 DFB_IN#
PIN TYPE
PWR
PWR
OUT
IN
IN
IN
PWR
PWR
IN
IN
IN
I/O
IN
IN
IN
IN
DESCRIPTION
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference for the differential current-mode output pairs.
It requires a fixed precision resistor to ground. 475ohm is the standard value
for 100ohm differential impedance. Other impedances require different values.
See data sheet.
Input to select operating frequency
1 = 100MHz, 0 = 133.33MHz
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
Notifies device to sample latched inputs and start up on first high assertion, or
exit Power Down Mode on subsequent assertions. Low enters Power Down
Mode.
Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated
as an analog power rail and filtered appropriately.
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the
SMB_A1 to decode 1 of 9 SMBus Addresses.
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the
SMB_A0 to decode 1 of 9 SMBus Addresses.
True half of differential feedback input, provides feedback signal to the PLL for
synchronization with the input clock to elimate phase error.
Complementary half of differential feedback input, provides feedback signal to
the PLL for synchronization with input clock to elimate phase error.
17 DFB_OUT#
OUT
Complementary half of differential feedback output, provides feedback signal
to the PLL for synchronization with input clock to eliminate phase error.
18 DFB_OUT
OUT
True half of differential feedback output, provides feedback signal to the PLL
for synchronization with the input clock to eliminate phase error.
19 DIF_0
OUT
0.7V differential true clock output
20 DIF_0#
OUT
0.7V differential Complementary clock output
21 VDD
PWR
Power supply, nominal 3.3V
22 DIF_1
OUT
0.7V differential true clock output
23 DIF_1#
OUT
0.7V differential Complementary clock output
24 DIF_2
OUT
0.7V differential true clock output
25 DIF_2#
OUT
0.7V differential Complementary clock output
26 GND
PWR
Ground pin.
27 DIF_3
OUT
0.7V differential true clock output
28 DIF_3#
OUT
0.7V differential Complementary clock output
29 DIF_4
OUT
0.7V differential true clock output
30 DIF_4#
OUT
0.7V differential Complementary clock output
31 VDD
PWR
Power supply, nominal 3.3V
32 DIF_5
OUT
0.7V differential true clock output
33 DIF_5#
OUT
0.7V differential Complementary clock output
34 OE5#
Active low input for enabling DIF pair 5.
IN 1 =disable outputs, 0 = enable outputs
35 DIF_6
OUT
0.7V differential true clock output
36 DIF_6#
OUT
0.7V differential Complementary clock output
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
1586P - 11/19/15
3










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