DataSheet26.com

853S111B PDF даташит

Спецификация 853S111B изготовлена ​​​​«IDT» и имеет функцию, называемую «3.3V LVPECL/ECL Fanout Buffer».

Детали детали

Номер произв 853S111B
Описание 3.3V LVPECL/ECL Fanout Buffer
Производители IDT
логотип IDT логотип 

25 Pages
scroll

No Preview Available !

853S111B Даташит, Описание, Даташиты
Low Skew, 1-to-10, Differential-to-2.5V,
3.3V LVPECL/ECL Fanout Buffer
853S111B
General Description
The 853S111B is a low skew, high performance 1-to-10
Differential-to-2.5V/ 3.3V LVPECL/ECL Fanout Buffer. The
853S111B is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the 853S111B ideal for those clock distribution
applications demanding well defined performance and repeatability.
Pin Assignments
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
24 23 22 21 20 19 18 17
25 16
26 853S111B 15
27 32-Lead TQFP, E-Pad 14
28 7mm x 7mm x 1mm 13
29 package body 12
30 Y Package 11
31 Top View 10
32 9
12 3 45 6 78
VCCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
VCCO
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
24 23 22 21 20 19 18 17
25 16
26 853S111B 15
27 32-Lead VFQFN 14
28 5mm x 5mm x 0.925mm 13
29 package body 12
30 K Package 11
31 Top View 10
32 9
12 3 45 6 78
VCCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
VCCO
Features
Ten differential 2.5V, 3.3V LVPECL/ECL outputs
Two selectable differential input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, SSTL, CML
Maximum output frequency: 2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 645ps (maximum)
Additive Phase Jitter, RMS: 0.03ps (typical)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) packaging
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
CLK_SEL Pulldown
VBB
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
nQ3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
nQ8
nQ8
Q9
nQ9
©2016 Integrated Device Technology, Inc.
1
Revision F, January 14, 2016









No Preview Available !

853S111B Даташит, Описание, Даташиты
853S111B Datasheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1 VCC Power
Positive supply pin.
Clock select input. When HIGH, selects PCLK1/nPCLK1 inputs. When
2
CLK_SEL
Input
Pulldown LOW, selects PCLK0/nPCLK0 inputs. LVPECL interface levels. Also
accepts standard LVCMOS input levels.
3
PCLK0
Input
Pulldown Non-inverting differential LVPECL clock input.
4
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
5 VBB Output
Bias voltage to be connected for single-ended applications.
6
PCLK1
Input
Pulldown Non-inverting differential LVPECL clock input.
7
nPCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
8
9, 16, 25, 32
10, 11
VEE
VCCO
nQ9, Q9
Power
Power
Output
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL/ECL interface levels.
12, 13
nQ8, Q8
Output
Differential output pair. LVPECL/ECL interface levels.
14, 15
nQ7, Q7
Output
Differential output pair. LVPECL/ECL interface levels.
17, 18
nQ6, Q6
Output
Differential output pair. LVPECL/ECL interface levels.
19, 20
nQ5, Q5
Output
Differential output pair. LVPECL/ECL interface levels.
21, 22
nQ4, Q4
Output
Differential output pair. LVPECL/ECL interface levels.
23, 24
nQ3, Q3
Output
Differential output pair. LVPECL/ECL interface levels.
26, 27
nQ2, Q2
Output
Differential output pair. LVPECL/ECL interface levels.
28, 29
nQ1, Q1
Output
Differential output pair. LVPECL/ECL interface levels.
30, 31
nQ0, Q0
Output
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
RPULLDOWN
RVCC/2
Input Pulldown Resistor
RPullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
k
k
©2016 Integrated Device Technology, Inc.
2
Revision F, January 14, 2016









No Preview Available !

853S111B Даташит, Описание, Даташиты
853S111B Datasheet
Function Tables
Table 3A. Clock Input Function Table
Inputs
PCLK0 or PCLK1 nPCLK0 or nPCLK1
01
10
0 Biased; NOTE 1
1 Biased; NOTE 1
Biased; NOTE 1
0
Biased; NOTE 1
1
Outputs
Q0:Q9
nQ0:nQ9
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
NOTE 1: Please refer to the Applications Information, “Wiring the Differential Input to Accept Single Ended Levels”.
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Table 3B. Control Input Function Table
Inputs
CLK_SEL
Selected Source
0 PCLK0, nPCLK0
1 PCLK1, nPCLK1
©2016 Integrated Device Technology, Inc.
3
Revision F, January 14, 2016










Скачать PDF:

[ 853S111B.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
853S111BLVPECL/ECL Fanout BufferIDT
IDT
853S111B3.3V LVPECL/ECL Fanout BufferIDT
IDT

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск