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8L30210 PDF даташит

Спецификация 8L30210 изготовлена ​​​​«IDT» и имеет функцию, называемую «Crystal or Differential to LVCMOS/LVTTL Clock Buffer».

Детали детали

Номер произв 8L30210
Описание Crystal or Differential to LVCMOS/LVTTL Clock Buffer
Производители IDT
логотип IDT логотип 

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8L30210 Даташит, Описание, Даташиты
Crystal or Differential to LVCMOS/
LVTTL Clock Buffer
8L30210
DATA SHEET
General Description
The 8L30210 is a low skew, 1-to-10 LVCMOS / LVTTL Fanout Buffer.
The low impedance LVCMOS/LVTTL outputs are designed to drive
50series or parallel terminated transmission lines.
The 8L30210 is characterized at full 3.3V and 2.5V, mixed 3.3V/2.5V,
3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output operating
supply modes. The input clock is selected from two differential clock
inputs or a crystal input. The differential input can be wired to accept
a single-ended input. The internal oscillator circuit is automatically
disabled if the crystal input is not selected.
Features
Ten LVCMOS / LVTTL outputs up to 200MHz
Differential input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Additive RMS phase jitter: 30fs (typical)
Synchronous output enable to avoid clock glitch
Power supply modes:
Core / Output
3.3V / 3.3V
2.5V / 2.5V
3.3V / 2.5V
3.3V / 1.8V
3.3V / 1.5V
2.5V / 1.8V
2.5V / 1.5V
Supports case temperature up to 105°C
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
32 31 30 29 28 27 26 25
Q0 1
24 Q9
VDDO 2
23 VDDO
00
Q1 3
22 Q8
GNDO 4
21 GNDO
01 8L30210
Q2 5
20 Q7
VDDO 6
19 VDDO
1x
Q3 7
18 Q6
Q4 8
17 Q5
9 10 11 12 13 14 15 16
8L30210 REVISION 2 11/24/15
32-pin, 5mm x 5mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.









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8L30210 Даташит, Описание, Даташиты
8L30210 DATA SHEET
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1
Q0 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
2
VDDO
Power
Output power supply pin for Bank A.
3
Q1 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
4
GNDO
Power
Power supply output ground.
5
Q2 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
6
VDDO
Power
Output power supply pin for Bank A.
7
Q3 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
8
Q4 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
9
GNDO
Power
Power supply output ground.
10
VDD Power
Power supply pin.
11
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input.
12
XTAL_OUT
Input
Crystal oscillator interface. XTAL_OUT is the output.
13
CLK0
Input Pulldown Non-inverting differential clock.
14
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock. Internal resistor bias to VDD/2.
15
GND
Power
Power supply core ground.
16
GNDO
Power
Power supply output ground.
17
Q5 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
18
Q6 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
19
VDDO
Power
Output power supply pin for Bank B.
20
Q7 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
21
GNDO
Power
Power supply output ground.
22
Q8 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
23
VDDO
Power
Output power supply pin for Bank B.
24
Q9 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
25
GNDO
Power
Power supply output ground.
26
GND
Power
Power supply core ground.
27
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock. Internal resistor bias to VDD/2.
28
CLK1
Input Pulldown Non-inverting differential clock.
29
SEL1
Input
Pulldown
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A.
30
SEL0
Input
Pulldown
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A.
31 OE Input Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 3B.
32
ePad
GNDO
Exposed Pad
Power
Power
Power supply output ground.
Must be connected to GND.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER
2
REVISION 2 11/24/15









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8L30210 Даташит, Описание, Даташиты
Table 2. Pin Characteristics
Symbol
Parameter
CLK[0:1],
CIN Input Capacitance nCLK[0:1],
SEL[1:0], OE
RPULLDOWN Input Pulldown Resistor
RPULLUP
Input Pullup Resistor
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
Test Conditions
VDDO = 3.465V
VDDO = 2.625V
VDDO = 1.95V
VDDO = 1.6V
VDDO = 3.3V ± 5%
VDDO = 2.5V ± 5%
VDDO = 1.8V ± 0.15V
VDDO = 1.5V ± 0.1V
8L30210 DATA SHEET
Minimum Typical Maximum Units
2 pF
51 k
51 k
11 pF
9 pF
8 pF
8 pF
40
40
50
55
REVISION 2 11/24/15
3 CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER










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