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PDF S-3530A Data sheet ( Hoja de datos )
| Número de pieza | S-3530A | |
| Descripción | REAL-TIME CLOCK | |
| Fabricantes | Seiko | |
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Rev. 1.3_00
REAL-TIME CLOCK
S-3530A
S-3530A is a CMOS real-time clock IC supporting an I2C-
BUS, which is designed to transfer or set each data of a clock
and calender as requested by a CPU. It provides connection
with a CPU via two wires and has two systems of an
interrupt/alarm features, allowing the alleviation of software
treatment on the side of a host.
It also works on lower power with the oscillating circuit
operated at a constant voltage.
Features
• Low power consumption:
0.7 µA typ. (VDD=3.0 V)
• Wide area of operating voltage: 1.7 to 5.5 V
• BCD input/output of year, month, day, day of a week, hour, minute and second
• CPU interface via two wires (I2C-BUS)
• Auto calender till the year of 2,099
(automatic leap year arithmetic feature included)
• Built-in power voltage detecting circuit
• Built-in constant voltage circuit
• Built-in flag generating circuit on power on/off
• Built-in alarm interrupter (two systems)
• Steady-state interrupt frequency/duty setting feature
• Built-in 32 kHz crystal oscillating circuit (Internal Cd, External Cg)
Applications
• Cellular phone
• PHS
• A variety of pagers
• TV set and VCR
• Games
Package
• 8-pin SSOP (pin pitch : 0.65 mm) (Package drawing code : FS008-A)
• Die
Seiko Instruments Inc.
1
1 page  
Rev.1.3_00
REAL-TIME CLOCK
S-3530A
Description of Pins
Pin No.
1
2
3
4
5
6
7
8
Symbol
INT1
XIN
XOUT
VSS
INT2
SCL
SDA
VDD
Table 1
Description
Configuration
Alarm interrupt 1 output pin.
Nch open drain output
Depending on the mode set by the INT1
(No protective diode on the
register and status register, it outputs low or side of VDD)
Clock when time is reached. It is disabled by
rewriting the status register.
Crystal oscillator connect pin (32,768 Hz)
(Internal Cd, External Cg)
−
Negative power supply pin (GND)
−
Alarm interrupt 2 output pin.
Nch open drain output
Depending on the mode set by the INT2
(No protective diode on the
register and status register, it outputs low or side of VDD)
Clock when time is reached. It is disabled by
rewriting the status register.
Serial clock input pin.
CMOS input (No protective
Follow the specification with great care to the diode on the side of VDD)
rising/falling time of the SCL signal because
the signal is treated at its rising/falling edge.
Serial data input/output pin.
Nch open drain output
This pin is usually pulled up to VDD via a
(No protective diode on the
resistor, and connected to other open-drain or side of VDD)
open-collector output devices in wired OR CMOS input
configuration.
Positive power supply pin.
−
Seiko Instruments Inc.
5
5 Page 
Rev.1.3_00
REAL-TIME CLOCK
S-3530A
1.7 Data reading
After a start condition is detected from the outside, the device code and command are received. At this
point, the real-time reading mode or status register reading mode is entered when the read/write bit is "1".
In either the real-time reading mode or status register reading mode, data are output in the order from LSB.
(1) Real-time data reading 1
S
TR
AE
R DEVICE Command A
T ADDRESS
D
SDA LINE
0 11 00 1 0 1
M LRA L
S S/CS
B BW K B
Real-time data
access 1 command
A
C
K
Year data
M
S
B
NO ACK from
Master Device
S
AT
CO
KP
LM
SS
BB
Second data
(2) Real-time data reading 2
S
TR
AE
R DEVICE Command A
T ADDRESS
D
SDA LINE
0 1 1 00 1 1 1
M LRA L
S S/CS
B BWK B
Real-time data
access 2 commands
Hour data
A
C
K
M
S
B
NO ACK from
Master Device
S
AT
CO
KP
LM
SS
BB
Second data
(3) Status register reading
S
T
A
R
T
R
E
DEVICE Command A
ADDRESS
D
SDA LINE
0 11 000 1 1
M LRA L
S S/CS
B BW K B
Status register
access command
NO ACK from
Master Device
M
S
B
Status data
S
T
O
P
Figure 10 Read communication
Caution
ACK Upside:
Generate from the master device
ACK Downside: Generate from the S-3530A
Seiko Instruments Inc.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S-3530A.PDF ] | |
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