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8V43FS92432 PDF даташит

Спецификация 8V43FS92432 изготовлена ​​​​«IDT» и имеет функцию, называемую «1360MHz Dual Output LVPECL Clock Synthesizer».

Детали детали

Номер произв 8V43FS92432
Описание 1360MHz Dual Output LVPECL Clock Synthesizer
Производители IDT
логотип IDT логотип 

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8V43FS92432 Даташит, Описание, Даташиты
1360MHz Dual Output LVPECL
Clock Synthesizer
8V43FS92432
DATA SHEET
General Description
The 8V43FS92432 is a 3.3V-compatible, PLL based clock
synthesizer targeted for high performance clock generation in
mid-range to high-performance telecom, networking, and computing
applications. With output frequencies from 21.25MHz to 1360MHz
and the support of two differential PECL output signals, the device
meets the needs of the most demanding clock applications.
The 8V43FS92432 is a programmable high-frequency clock source
(clock synthesizer). The internal PLL generates a high-frequency
output signal based on a low-frequency reference signal. The
frequency of the output signal is programmable and can be changed
on the fly for frequency margining purpose.
The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. Alternatively, a LVCMOS compatible
clock signal can be used as a PLL reference signal. The frequency of
the internal crystal oscillator is divided by a selectable divider and
then multiplied by the PLL. Its output is scaled by a divider that is
configured by either the I2C or parallel interfaces. The crystal
oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider
M, and the PLL post-divider N determine the output frequency. The
feedback path of the PLL is internal.
The PLL post-divider N is configured through either the I2C or the
parallel interfaces, and can provide one of six division ratios (2, 4, 8,
16, 32, 64). This divider extends the performance of the part while
providing a 50% duty cycle. The high-frequency outputs, QA and QB,
are differential and are capable of driving a pair of transmission lines
terminated 50to VCC – 2.0 V. The second high-frequency output,
QB, can be configured to run at either 1x or 1/2x of the clock
frequency or the first output (QA). The positive supply voltage for the
internal PLL is separated from the power supply for the core logic
and output drivers to minimize noise induced jitter.
The configuration logic has two sections: I2C and parallel. The
parallel interface uses the values at the M[9:0], NA[2:0], NB, and P
parallel inputs to configure the internal PLL dividers. The parallel
programming interface has priority over the serial I2C interface. The
serial interface is I2C compatible and provides read and write access
to the internal PLL configuration registers. The lock state of the PLL
is indicated by the LVCMOS-compatible LOCK output.
Features
21.25MHz to 1360MHz synthesized clock output signal
Two differential, LVPECL-compatible high-frequency outputs
Output frequency programmable through 2-wire I2C bus or
parallel interface
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference clock input
Synchronous clock stop functionality for both outputs
LOCK indicator output (LVCMOS)
LVCMOS compatible control inputs
Fully integrated PLL
3.3-V power supply
48-lead LQFP
48-lead Pb-free package available
SiGe Technology
Ambient temperature range: –40°C to +85°C
Applications
Programmable clock source for server, computing, and
telecommunication systems
Frequency margining
Oscillator replacement
8V43FS92432 REVISION 1 10/28/15
1 ©2015 INTEGRATED DEVICE TECHNOLOGY, INC.









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8V43FS92432 Даташит, Описание, Даташиты
8V43FS92432 DATA SHEET
Block Diagram
REF_CLK
XTAL1
XTAL2
REF_SEL
TEST_EN
SDA
SCL
ADR[1:0]
nPPLLOOAADD
M[9:0]
NA[2:0]
NB
P
nCLKC_SLKTO_SPT[OA:PBx]
nBBYYPPAASSSS
nMMRR
÷P
OSC fREF
PLL
Configuration
Registers
I2C Control
PLL fVCO
÷NA
fQA
QA
fQB
÷NB
QB
÷M
LOCK
Pin Assignment
It is recommended to use an external RC filter for the analog
VCC_PLL supply pin. Please see the application section for details.
GND
NA2
NA1
NA0
nPLOAD
VCC
nMR
SDA
SCL
ADR1
ADR0
P
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 21
41 20
42 19
43 18
44 17
45 16
46 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
M9
M8
M7
M6
M5
GND
M4
M3
M2
M1
M0
VCC
48-pin, 7mm x 7mm LQFP Package
1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
2
REVISION 1 10/28/15









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8V43FS92432 Даташит, Описание, Даташиты
8V43FS92432 DATA SHEET
Pin Description and Characteristic Tables
Table 1. Pin Description Table
Number
Name
Type1
Description
1 VCC Power
2
nBYPASS
Input
Pullup
Positive supply for I/O and core.
Selects the static circuit bypass mode.
3
GND
Power
Power supply ground.
4 VCC Power
5
VCC_PLL
Power
6
REF_SEL
Input
Pullup
Positive supply for I/O and core.
Positive power supply for the PLL (analog power supply). It is recommended
to use an external RC filter for the analog power supply pin VCC_PLL.
Selects the reference clock input.
7
REF_CLK
Input
Pulldown
PLL external single-ended reference input. LVCMOS/LVTTL interface levels.
8
GND
Power
Power supply ground.
9 nCLK_STOPA Input
Pullup
Output Qx disable in logic low state.
10 nCLK_STOPB Input
Pullup
Output Qx disable in logic low state.
11
XTAL1
Crystal
Input
Crystal input.
12
XTAL2
Crystal
Output
Crystal output.
13 VCC Power
Positive supply for I/O and core.
14
M0
Input
Pulldown
PLL feedback divider configuration.
15
M1
Input
Pulldown
PLL feedback divider configuration.
16
M2
Input
Pullup
PLL feedback divider configuration.
17
M3
Input
Pulldown
PLL feedback divider configuration.
18
M4
Input
Pullup
PLL feedback divider configuration.
19
GND
Power
Power supply ground.
20
M5
Input
Pullup
PLL feedback divider configuration.
21
M6
Input
Pullup
PLL feedback divider configuration.
22
M7
Input
Pullup
PLL feedback divider configuration.
23
M8
Input
Pullup
PLL feedback divider configuration.
24
M9
Input
Pulldown
PLL feedback divider configuration.
25
TEST_EN
Input
Pulldown
Factory test mode enable. This input must be set to logic low level in all
applications of the device.
26
LOCK
Output
LVCMOS
PLL lock indicator.
27
GND
Power
Power supply ground.
28
nQB
Output
LVPECL
High frequency clock output.
29
QB
Output
LVPECL
High frequency clock output.
30 VCC Power
31
GND
Power
Positive supply for I/O and core.
Power supply ground.
32
nQA
Output
LVPECL
High frequency clock output.
33
QA
Output
LVPECL
High frequency clock output.
REVISION 1 10/28/15
3 1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER










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