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HI-2130 PDF даташит

Спецификация HI-2130 изготовлена ​​​​«HOLTIC» и имеет функцию, называемую «3.3V BC / MT / RT».

Детали детали

Номер произв HI-2130
Описание 3.3V BC / MT / RT
Производители HOLTIC
логотип HOLTIC логотип 

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HI-2130 Даташит, Описание, Даташиты
October 2016
HI-2130
Single Package MIL-STD-1553 / MIL-STD-1760
3.3V BC / MT / RT with Integrated Transformers
GENERAL DESCRIPTION
The HI-2130 provides a 3.3V fully integrated interface
between a host processor and a MIL-STD-1553 /
MIL-STD-1760 bus. It combines the functionality of Holt’s
HI-6130 16-bit parallel bus interface and HI-6131 SPI
devices, integrating MIL-STD-1553 protocol logic, dual
transceivers and dual transformers in a single compact
15 x 15 x 4.4 mm package; the smallest 1553 terminal
solution with integrated magnetics in a single package.
Both RoHS compliant and Sn/Pb configurations are
available, giving customers a solution for tin-lead
assemblies while avoiding expensive re-balling.
The device includes the entire signal I/O set of HI-6130
and HI-6131, with the addition of a new input signal for
selecting parallel bus or SPI host interface. Two pairs
of transformer output signals connect directly to the
MIL-STD-1553 Bus A and Bus B stubs.
The part is available in Industrial -40oC to +85oC, or
Extended, -55oC to +125oC temperature ranges.
Refer to the HI-6130 datasheet for full functional
description and operation.
64K Byte
Shared RAM
BC RT
RT MT
MIL-STD-1553 Protocol &
Memory Management
External Serial
Flash EEPROM
Interface
HI-2130
Transformers
Transceiver
A
Transceiver
B
FEATURES
Combined functionality of HI-6130 and HI-6131
in a single package with integrated transformers
Smallest footprint MIL-STD-1553 solution
available (includes transformers)
• Low profile package solution suitable for PMC
and XMC applications
Extended temperature range, -55ºC to +125ºC
Hermetically sealed die option (MSL 1) available
Less expensive than traditional multi-chip
modules
• DO-254 certifiable
Concurrent multi-terminal operation (BC, MT, 1 or
2 independent RTs)
Two host interface options in one package: 16-bit
parallel bus or 4-wire SPI
64K bytes on-chip RAM with error detection/
correction option
Autonomous terminal operation requires minimal
host intervention
Shared MIL-STD-1553 bus interface reduces
circuit complexity and circuit board area.
Fully programmable Bus Controller with 28 op
code instruction set
Simple Monitor Terminal (SMT) Mode records
commands and data separately, with 16-bit or
48-bit time tagging
IRIG Monitor Terminal (IMT) Mode supports
IRIG-106 Chapter 10 packet format. Complete
IRIG-106 data packets including full packet
headers and trailers can be generated
Independent time-tag counters for all terminals
with 32-bit option for Bus Controller and 48-bit
option for Monitor Terminal
64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources
Built-in self-test for protocol logic, digital signal
paths and internal RAM
Optional self-initialization at reset uses external
serial EEPROM
Two temperature ranges: -40oC to +85oC, or
-55oC to +125oC
DS2130 Rev. H
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
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HI-2130 Даташит, Описание, Даташиты
BLOCK DIAGRAM
HI-2130
IRQ
MTPKRDY
READY
ACTIVE
RT1MC8
RT2MC8
BWID
BTYPE
WPOL
WE
OE
A0
WAIT
A15:1
D15:0
BUS / SPI
CE
SCK
MOSI
MISO
AUTOEN
EECOPY
MR
BCENA
BCTRIG
MTRUN
RT1ENA
RT2ENA
ACKIRQ
RT1SSF
RT2SSF
HI-6130 / HI-6131
HI-2130
Discrete
Signal
Outputs
64K
Static RAM
and
Registers
Host
Interface
Address
Data
Control
Memory
and
Register
Access
Control
BC
Message
Processor
MT
Message
Processor
Configuration
Option
Logic
INTERNAL
CLOCKS
Bus A
Manchester
Encoder
Bus A
Manchester
Decoder
Reset &
Initialization
Logic
Discrete
Signal
Inputs
Serial
Peripheral
Interface
(SPI) to
EEPROM
RT1
Message
Processor
RT2
Message
Processor
Bus B
Manchester
Encoder
Bus B
Manchester
Decoder
POWER
Test
Logic
RT1A4 - 0
RT1AP
RT2A4 - 0
RT2AP
BENDI
RT1LOCK
RT2LOCK
MTSTOFF
RAMEDC
MCLK
TTCLK
MTTCLK
TXINHA
BUSA
BUSA
TXINHB
BUSB
BUSB
GND
VDD
TEST
MODE
OPTIONAL
SERIAL EEPROM
(AUTO-CONFIG)
HOLT INTEGRATED CIRCUITS
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HI-2130 Даташит, Описание, Даташиты
PIN DIAGRAM
HI-2130
Top View
11 10 9 8 7 6 5 4 3 2 1
L
RAM
EDC
DATA DATA DATA DATA
14 11
9
4
RT1 MTPKT RT1
SSF RDY MC8
nIRQ
B
TYPE
BENDI
L
K
nCE
DATA
12
DATA AUTO DATA
10 EN
6
VDD
AC-
TIVE
ACK
IRQ
DATA
2
WPOL
nBUS
A
K
J
MODE
BC
TRIG
DATA
13
TX
INHA
DATA
7
DATA
5
READY
TEST
DATA
0
DATA nBUS
1A
J
H
MISO
DATA
15
MOSI
TX
INHB
DATA
8
DATA
3
RT2
MC8
MTST RT1
OFF LOCK
DNC
BUS
A
H
G
nWAIT SCLK nOE
VDD
GND
VDD
GND
VDD
BC
ENA
DNC
BUS
A
G
F
nWE
BUS
nSPI
MCLK
GND
VDD
GND
VDD
GND
VDD
DNC
DNC
F
E
RT1
A2
RT1
A0
RT1
A1
VDD GND VDD GND VDD
RT2
ENA
DNC
BUS
B
E
D
nMR
RT1
A3
RT1
A4
ADDR
8
nECS
ADDR
10
RT2
LOCK
RT2
A0
RT2
A1
DNC
BUS
B
D
C
ADDR
0
RT1
ENA
ADDR E
2 MOSI
GND
EE
COPY
MT
RUN
RT2
A2
RT2 ADDR nBUS
A3 14
B
C
B
ADDR ADDR ADDR ADDR TT
1 3 4 6 CLK
VDD
ESCK
RT2
SSF
ADDR ADDR nBUS
13 15
B
B
A
ADDR RT1 E ADDR MTT ADDR ADDR RT2
5 AP MISO 7 CLK 9 11 AP
RT2
A4
ADDR
12
BWID
A
11 10 9 8 7 6 5 4 3 2 1
See HI-6130 datasheet for a full Pin Description.
Notes:
a. DNC: Do Not Connect.
b. All balls denoted VDD must be connected to 3.3V DC power.
c. All balls denoted GND must be connected to circuit ground.
d. BUS/nSPI (F10) selects 16-bit wide parallel bus or SPI operation (see Section “Selection of Host Interface” on
page 4).
e. nCE: The chip enable signal is shared between 16-bit parallel and SPI host interfaces (SPI Slave Select).
HOLT INTEGRATED CIRCUITS
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