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HI-3588 PDF даташит

Спецификация HI-3588 изготовлена ​​​​«HOLTIC» и имеет функцию, называемую «Receiver».

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Номер произв HI-3588
Описание Receiver
Производители HOLTIC
логотип HOLTIC логотип 

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HI-3588 Даташит, Описание, Даташиты
July 2012
HI-3588
ARINC 429
Receiver with SPI Interface
GENERAL DESCRIPTION
The HI-3588 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to an ARINC 429 serial bus.
The device provides one receiver with user-programmable
label recognition for any combination of 256 possible
labels, a 32 by 32 Receive FIFO and an analog line
receiver. Receive FIFO status can be monitored using the
programmable external interrupt pin, or by polling the
HI-3588 Status Register. Other features include the ability
to switch the bit-signifiance of ARINC 429 labels. The
ARINC input pins are available with different input resis-
tance values to provide flexibility when adding external
lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals allowing for a small footprint device
which can be interfaced to a wide variety of industry-
standard microcontrollers supporting SPI. Alternatively,
the SPI signals may be controlled using just four general
purpose I/O port pins from a microcontroller or custom
FPGA. The SPI and all control signals are CMOS and TTL
compatible and support 3.3V or 5V operation.
The HI-3588 checks received data against ARINC 429
electrical, timing and protocol requirements. ARINC 429
databus timing comes from a 1 MHz clock input,
or an internal counter can derive it from higher clock
frequencies having certain fixed values, possibly the
external host processor clock.
FEATURES
· ARINC specification 429 compliant
· 3.3V or 5.0V logic supply operation
· On-chip analog line receiver connects directly to
ARINC 429 bus
· Programmable label recognition for 256 labels
· 32 x 32 Receive Data FIFO
· Programmable data rate selection
· High-speed, four-wire Serial Peripheral Interface
· Label bit-order control
· Parity checking may be disabled to allow 32-bit data
reception
· Low power
· Industrial & extended temperature ranges
PIN CONFIGURATIONS (Top View)
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
CS - 9
N/C - 10
N/C - 11
HI-3588PCI
HI-3588PCT
33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - N/C
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
CS - 9
N/C - 10
N/C - 11
HI-3588PQI
HI-3588PQT
33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - N/C
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3588 Rev. G)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/12









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HI-3588 Даташит, Описание, Даташиты
BLOCK DIAGRAM
HI-3588
VDD
ACLK
ARINC
Clock
Divider
SCK
CS
SI
SO
RINA-40
RINB-40
RINA
RINB
SPI
Interface
Control Register
Status Register
40 Kohm
40 Kohm
ARINC 429
Line Receiver
ARINC 429
Valid word
Checker
Label
Filter
Bit Map
Memory
Label
Filter
ARINC 429
Received
Data FIFO
GND
RFLAG
PIN DESCRIPTIONS
SIGNAL
RINB
RINB-40
MR
SI
CS
SCK
GND
ACLK
SO
RFLAG
VDD
RINA-40
RINA
FUNCTION
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
POWER
INPUT
OUTPUT
OUTPUT
POWER
INPUT
INPUT
DESCRIPTION
ARINC receiver negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver negative input. Requires external 40K ohm resistor
Master Reset. A positive pulse clears the Receiver data FIFO and flags
SPI interface serial data input
Chip select. Data is shifted into SI and out of SO when CS is low.
SPI Clock. Data is shifted into or out of the SPI interface using SCK
Chip 0V supply. Note BOTH GND pins MUST be connected
Master timing source for the ARINC 429 receiver
SPI interface serial data output
Goes high when ARINC 429 receiver FIFO is empty (CR15=0), or full (CR15=1)
3.3V or 5.0V logic power
Alternate ARINC receiver positive input. Requires external 40K ohm resistor
ARINC receiver positive input. Direct connection to ARINC 429 bus
INTERNAL PULL UP / DOWN
10K ohm pull-down
10K ohm pull-down
10K ohm pull-up
10K ohm pull-down
10K ohm pull-down
HOLT INTEGRATED CIRCUITS
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HI-3588 Даташит, Описание, Даташиты
HI-3588
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI-
3588A. When CS goes low, the next 8 clocks at the SCK pin shift
an instruction op code into the decoder, starting with the first
positive edge. The op code is fed into the SI pin, most significant bit
first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit writes to Control Register,
32-bit ARINC word writes to transmit FIFO or 256-bit writes to the
label-matching enable/disable table.
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
data field bit-length varies with read instruction type.
Table 1 lists all instructions. Instructions that perform a reset or set
are executed after the last SI bit is received while CS is still low.
Example:
one SPI Instruction
CS
SCK
SI
op code 07hex
data field 02hex
MSB
LSB MSB
LSB
TABLE 1. DEFINED INSTRUCTION OP CODES
OP CODE
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
DATA FIELD
None
None
None
None
8 bits
8 bits
256 bits
8 bits
32 bits
None
8 bits
16 bits
8 bits
256 bits
None
None
16 bits
DESCRIPTION
No instruction implemented
After the 8th op-code bit is received, perform Master Reset (MR)
After the 8th op-code bit is received, reset all label selections
After the 8th op-code bit is received, set all the label selections
Reset label at address specified in data field
Set label at address specified in data field
Starting with label FF hex, consecutively set or reset each label in descending order
For example, a Data Field pattern starting with 1011 will set labels FF, FD, and
FC hex and reset label FE hex.
Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC receiver operates from the divided ACLK clock. Allowable
values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in
no clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock.
Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros
No instruction implemented
Read the Status Register
Read the Control Register
Read the ACLK divide value programmed previously using op code 07 hex
Read the Label look-up memory table consecutively starting with address FF hex
No instruction implemented
No instruction implemented
Write the Control Register
HOLT INTEGRATED CIRCUITS
3










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