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PDF HI-6137 Data sheet ( Hoja de datos )
| Número de pieza | HI-6137 | |
| Descripción | Compact Multi-Terminal Device | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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November, 2016
MAMBATM: HI-6137
3.3V BC / RT MIL-STD-1553 / MIL-STD-1760
Compact Multi-Terminal Device with SPI Host Interface
GENERAL DESCRIPTION
The 3.3V CMOS HI-6137 device is a member of
Holt’s MIL-STD-1553 MAMBATM family and provides
a complete single- or multi-function interface between
a host processor and MIL-STD-1553B bus. Each IC
contains a Bus Controller (BC) and a Remote Terminals
(RT). Any combination of the contained 1553 functions
can be enabled for concurrent operation. The enabled
terminals communicate with the MIL-STD-1553 buses
through a shared on-chip dual bus transceiver and
external transformers. The user allocates 16K bytes of
on-chip static RAM between devices to suit application
requirements.
• Built-in self-test for protocol logic, digital signal
paths and internal RAM.
• Optional self-initialization at reset uses external
serial EEPROM.
• ±8kV ESD Protection (HBM, all pins).
• Two temperature ranges: -40oC to +85oC, or
-55oC to +125oC with optional burn-in.
• RoHS compliant and Tin / Lead options available.
PIN CONFIGURATION (TOP)
The HI-6137 communicates with the host via a 40 MHz
4-wire serial peripheral interface (SPI). Programmable
interrupts provide terminal status to the host processor.
Circular data buffers in RAM have interrupts for rollover
and programmable “level attained”.
The HI-6137 can be configured for automatic self-
initialization after reset. A dedicated SPI port reads
data from an external serial EEPROM to fully configure
registers and RAM and optionally start execution for any
of the terminal devices.
MODE - 1
IRQ - 2
ACKIRQ - 3
MODE1760 - 4
READY - 5
VCC - 6
GND - 7
ACTIVE - 8
RTSSF - 9
AUTOEN - 10
TXINHA - 11
TXINHB - 12
HI-6137PCIF
HI-6137PCTF
HI-6137PCMF
36 - TTCLK
35 - ESCLK
34 - EECOPY
33 - ECS
32 - MOSI
31 - VCC
30 - GND
29 - MISO
28 - TESTB
27 - LOCK
26 - RTA4
25 - RTA3
FEATURES
• Concurrent multi-terminal operation for BC and/or
RT MIL-STD-1553B functions.
• 8K x 17-bit words internal static RAM with parity
• Autonomous terminal operation requires minimal
host intervention.
• 40 MHz SPI Host Interface.
• MIL-STD-1760 option sets Busy bit in Status
Word response during initialization.
• World’s smallest MIL-STD-1553 terminal, QFN
package measures just 6mm x 6mm.
• Fully programmable Bus Controller with 28 op
code instruction set.
• Independent 16-bit time tag counters and clock
sources for all modes. The Bus Controller also
has 32- and 48-bit time count options.
• 64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources.
48 - Pin Plastic 6mm x 6mm
Chip-Scale Package (QFN)
See Section 24.1 on page 226 for 48-Pin PQFP Configuration
DS6137 Rev. D
HOLT INTEGRATED CIRCUITS
www.holtic.com
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1 page  
HI-6137
11.9. Bus Controller (BC) Time Tag Counter (0x0043)....................................................... 88
11.10. Bus Controller (BC) Time Tag Counter High (0x0044)............................................... 88
11.11. Bus Controller (BC) Time Tag Utility Register (0x0045) ............................................ 89
11.12. Bus Controller (BC) Time Tag Utility High Register (0x0046) ................................... 89
11.13. Bus Controller (BC) Time Tag Match Register (0x0047) ........................................... 89
11.14. Bus Controller (BC) Time Tag Match High Register (0x0048) .................................. 89
11.15. Bus Controller Interrupt Registers and Their Use...................................................... 89
11.15.1. Bus Controller (BC) Interrupt Enable Register (0x0010) ....................................... 91
11.15.2. Bus Controller (BC) Pending Interrupt Register (0x0007) ..................................... 91
11.15.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014) ........................... 91
12. REMOTE TERMINAL − OVERVIEW ............................................................... 94
13. REMOTE TERMINAL REGISTERS.................................................................. 95
13.1. Remote Terminal Configuration Register (0x0017) ................................................... 95
13.2. Remote Terminal Operational Status Register (0x0018) .......................................... 99
13.3. Remote Terminal Current Command Register (0x0002).......................................... 101
13.4. Remote Terminal Current Control Word Address Register (0x0003) ...................... 101
13.5. Remote Terminal Descriptor Table Base Address Register (0x0019)...................... 101
13.6. Remote Terminal MIL-STD-1553 Status Word Bits Register (0x001A).................... 102
13.7. Remote Terminal Current Message Information Word Register (0x001B)............... 103
13.8. Remote Terminal Bus A Select Register (0x001C).................................................. 104
13.9. Remote Terminal Bus B Select Register (0x001D).................................................. 104
13.10. Remote Terminal Built-In Test (BIT) Word Register (0x001E).................................. 105
13.11. Remote Terminal Alternate Built-In Test (BIT) Word Register (0x001F)................... 106
13.12. Remote Terminal Time Tag Counter Register (0x0049)........................................... 106
13.13. Remote Terminal Time Tag Utility Register (0x004A)............................................... 107
13.13.1. RT Time Tag Counter Loading ............................................................................. 107
13.13.2. RT Time Tag Count Match Interrupts ................................................................... 107
13.14. Remote Terminal Interrupt Registers and Their Use................................................ 108
13.14.1. Remote Terminal (RT) Interrupt Enable Register (0x0012).................................. 109
13.14.2. Remote Terminal (RT) Pending Interrupt Register (0x0009)................................ 109
13.14.3. Remote Terminal (RT) Interrupt Output Enable Register (0x0016)...................... 109
14. REMOTE TERMINAL CONFIGURATION AND OPERATION......................... 112
14.1. Command Responses............................................................................................. 112
14.1.1. RT to RT Commands. .......................................................................................... 114
HOLT INTEGRATED CIRCUITS
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5 Page 
HI-6137
List of Tables
Table 1. Pin Descriptions.............................................................................................................. 14
Table 2. Host Interface Pins.......................................................................................................... 16
Table 3. Register Summary.......................................................................................................... 22
Table 4. Bus Controller Condition Code Table.............................................................................. 52
Table 5. Bus Controller Instruction Op Codes.............................................................................. 55
Table 6. Effect of “Broadcast Command Received” RT Status Bit on “Status Set” Condition...... 83
Table 7. Summary of Data Buffer Modes. .................................................................................. 136
Table 8. Circular Buffer Mode 2 (Initialization factors based on message block size)................ 158
Table 9. Mode Code Command Summary................................................................................. 163
Table 10. Terminal Unlock Word Encoding................................................................................. 168
Table 11. Registers are not written using EEPROM data........................................................... 169
Table 12. READY delay times: from MR input pin rising edge to READY output pin rising edge.....
171
Table 13. RT Soft Reset Summary............................................................................................. 175
Table 14. Fast-Access SPI Commands for Lower Registers ..................................................... 193
Table 15. SPI Commands using Memory Address Pointer......................................................... 194
HOLT INTEGRATED CIRCUITS
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HI-6137.PDF ] | |
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