PDF CD40208BMS Data sheet ( Hoja de datos )

Número de pieza	CD40208BMS
Descripción	CMOS 4 x 4 Multiport Register
Fabricantes	Intersil Corporation
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CD40208BMS December 1992 CMOS 4 x 4 Multiport Register Features Description • High Voltage Types (20V Rating) • One Input and Two Output Buses • Unlimited Expansion in Bit and Word Directions • Data Lines have Latched Inputs • 3-State Outputs • Separate Control of Each Bus, Allowing Simultaneous Independent Reading of any of Four Registers on Bus A and Bus B and Independent Writing Into any of the Four Registers • 100% Tested for Quiescent Current at 20V • Standardized, Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Pack- age-Temperature Range; 100nA at 18V and +25oC • Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Stan- dards No. 13B, “Standard Speciﬁcations for Descrip- tion of “B” Series CMOS Devices” Applications • Scratch Pad Memories • Arithmetic Units • Data Storage The CD40208BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high imped- ance state. The high impedance third state provides the out- puts with the capability of being connected to the bus lines in a bus organized system without the need for interface or pull-up components. When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and no new data is entered. In either case, the contents of any word may be accessed via the read address lines inde- pendent of the state of the CLOCK input. The CD40208BMS types are supplied in hermetic 24-lead dual-in-line ceramic packages (D and F sufﬁxes), 24-lead dual-in-line plastic packages (E sufﬁx), 24-lead ceramic ﬂat packages (K sufﬁx), and in chip form (H sufﬁx). The CD40208BMS is supplied in these 24-lead outline pack- ages: Braze Seal DIP HNZ Ceramic Flatpack H4P Pinout CD40208BMS TOP VIEW Q3B 1 Q2B 2 ENABLE A 3 Q0A 4 Q1A 5 Q2A 6 Q3A 7 WRITE 0 8 WRITE 1 9 READ 0B 10 READ 1B 11 VSS 12 24 VDD 23 Q1B 22 Q0B 21 ENABLE B 20 D0 19 D1 18 D2 17 D3 16 CLOCK 15 WRITE ENABLE 14 READ 1A 13 READ 0A Functional Diagram WRITE ENABLE ENABLE A DATA INPUTS 20 D0 19 D1 18 D2 17 D3 15 3 4 Q0 5 Q1 6 Q2 7 Q3 WRITE 0 WRITE 1 8 9 14 READ 1A 13 READ 0A 11 READ 1B 10 READ 0B 22 Q0 23 Q1 2 Q2 1 Q3 VDD = 24 VSS = 12 16 21 CLOCK ENABLE B WORD A OUTPUT WORD B OUTPUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Copyright © Intersil Corporation 1999 7-1431 File Number 3396 1 page Speciﬁcations CD40208BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS Maximum Clock Input Frequency FCL VDD = 10V VDD = 15V Clock Rise and Fall Time tRCL tFCL VDD = 5V VDD = 10V VDD = 15V Transition Time TTHL TTLH VDD = 10V VDD = 15V Input Capacitance CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 3.5 4.5 - - - - - - MAX - - 15 5 5 100 80 7.5 UNITS MHz MHz µs µs µs ns ns pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K., Input TR, TF < 20ns 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VNTH VDD = 10V, ISS= -10µA VPTH VSS = 0V, IDD = 10µA ∆VPTH VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 2, 3, 4 TEMPERATURE +25oC +25oC +25oC MIN - -2.8 - MAX 25 -0.2 ±1 +25oC +25oC 0.2 2.8 - ±1 +25oC +25oC VOH > VOL < VDD/2 VDD/2 - 1.35 x +25oC Limit NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input tR, tF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record. UNITS µA V V V V V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 Output Current (Sink) Output Current (Source) IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading 7-1435 5 Page CD40208BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Ofﬁce Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 1441 11 Page

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