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PDF AS5SP128K36 Data sheet ( Hoja de datos )
| Número de pieza | AS5SP128K36 | |
| Descripción | Synchronous SRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
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Plastic Encapsulated Microcircuit
4.5Mb, 128K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
• RoHs compliant options available
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM
AS5SP128K36
SSRAM [SPB]
80 DQPb
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 DQPa
FAST ACCESS TIMES
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
❑ Synchronous Pipeline
Burst
❋ Two (2) cycle load
❋ One (1) cycle
de-select
❋ One (1) cycle latency
on Mode change
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
GENERAL DESCRIPTION
The AS5SP128K36 is a 4.5Mb High Performance Synchronous
Pipeline Burst SRAM, available in multiple temperature
screening levels, fabricated using High Performance CMOS
technology and is organized as a 128K x 36. It integrates
address and control registers, a two (2) bit burst address
counter supporting four (4) double-word transfers. Writes are
internally self-timed and synchronous to the rising edge of
clock.
Output Output
Register Driver
Input
Register
The AS5SP128K36 includes advanced control options
including Global Write, Byte Write as well as an Asynchronous
Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
DQx, DQPx Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
AS5SP128K36
Rev. 1.6 10/13
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
SSRAM
AS5SP128K36
SYNCHRONOUS TRUTH TABLES
CE1\
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
Notes:
CE2
CE3\ ADSP\ ADSC\ ADV WT / RD
XXXLXX
LXLXXX
XH L XXX
LXXLXX
XHX LXX
HL LXXX
H L H L X WT
H L H L X RD
X X H H L RD
X X X H L RD
X X H H L WT
X X X H L WT
X X H H H RD
X X X H H RD
X X H H H WT
X X X H H WT
1. X = Don’t Care
2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE
CLK
Address Accessed
NA
NA
NA
NA
NA
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Operation
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst, READ
Begin Burst, WRITE
Begin Burst, READ
Continue Burst, READ
Continue Burst, READ
Continue Burst, WRITE
Continue Burst, WRITE
Suspend Burst, READ
Suspend Burst, READ
Suspend Burst, WRITE
Suspend Burst, WRITE
BURST SEQUENCE TABLES
CAPACITANCE
Burst Control
Pin [MODE]
First Address
State
HIGH
Fourth Address
Case 1
A1 A0
0
0
1
1
Interleaved Burst
Case 2
A1 A0
00
10
01
11
1
0
1
0
Case 3
A1 A0
1
1
0
0
0
1
0
1
Case 4
A1 A0
1
1
0
0
1
0
1
0
Parameter
Input Capacitance
Input/Output Capacitance
Clock Input Capacitance
Symbol
CI
CIO
CCLK
Max.
6
8
6
Units
pF
pF
pF
Burst Control
Pin [MODE]
First Address
State
LOW
Fourth Address
Case 1
A1 A0
0
0
1
1
Linear Burst
Case 2
A1 A0
00
11
01
10
1
0
1
0
Case 3
A1 A0
1
1
0
0
0
1
0
1
Case 4
A1 A0
1
0
0
1
1
0
1
0
WRITE TABLE
GW\
H
H
H
H
H
H
L
BW\
H
L
L
L
L
L
X
BWa\
X
H
L
H
H
L
X
BWb\
X
H
H
L
H
L
X
BWc\
X
H
H
H
L
L
X
BWd\
X
H
H
H
L
L
X
Operation
READ
READ
WRITE Byte [A]
WRITE Byte [B]
WRITE Byte [C], [D]
WRITE ALL Bytes
WRITE ALL Bytes
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ OE\
Power-Down (SLEEP)
H
X
READ
LL
LH
WRITE
LX
De-Selected
LX
I/O Status
High-Z
DQ
High-Z
Din, High-Z
High-Z
AC TEST LOADS
ABSOLUTE MAXIMUM RATINGS*
Absolute Maximum Ratings
Parameter
Symbol Min.
Max.
Voltage on VDD Pin
Voltage on VDDQ Pins
Voltage on Input Pins
Voltage on I/O Pins
Power Dissipation
Storage Temperature
Operating Temperatures
[Screening Levels]
VDD
VDDQ
VIN
VIO
PD
tSTG
/IT
/ET
/XT
-0.3
VDD
-0.3
-0.3
-65
-40
-40
-55
4.6
VDD+0.3
VDDQ+0.3
1.6
150
85
105
125
Units
V
V
V
V
W
RC
RC
RC
RC
*Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause per-
manent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions greater than those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum conditions for any
duration or segment of time may affect device reliability.
Output
Zo=50 ohm
Rt = 50 ohm
Diagram [A] 30 pF
Vt= Termination Voltage
Rt= Termination Resistor
Vt= 1.50v for 3.3v VDDQ
Vt= 1.25v for 2.5v VDDQ
3.3/2.5v
R= 351 [email protected]
R= 1538 [email protected]
R= 317 [email protected]
R= 1667 [email protected]
Output
5 pF
Diagram [B]
AS5SP128K36
Rev. 1.6 10/13
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
SSRAM
AS5SP128K36
POWER DOWN (SNOOZE MODE)
Power Down or Snooze is a Power conservation mode
which when building large/very dense arrays, using
multiple devices in a multi-banked or paged array, can
greatly reduce the Operating current requirements of
your total memory array solution.
The device is placed in this mode via the use of the ZZ
pin, an asynchronous control pin which when asserted,
places the array into the lower power or Power Down
mode. Awakening the array or leaving the Power Down
(SNOOZE) mode is done so by deasserting the ZZ pin .
While in the Power Down or Snooze mode, Data integ-
rity is guaranteed. Accesses pending when the device
entered the mode are not considered valid nor is the
completion of the operation guaranteed. The device
must be de-selected prior to entering the Power Down
mode, all Chip Enables, ADSP\ and ADSC\ must remain
inactive for the duration of ZZ recovery time (tZZREC).
ZZ MODE ELECTRICAL CHARACTERISTICS
Parameter
Power Down (SNOOZE) Mode
ZZ Active (Signal HIGH) to Power Down
ZZ Inactive (Signal Low) to Power Up
Symbol
Test Conditon
IDDzz ZZ >/- VDD - 0.2V
tZZS
ZZ >/- VDD - 0.2V
tZZR
ZZ </- 0.2V
Min.
2 tCYC
Max.
70
2 tCYC
Units
mA
ns
ns
ZZ MODE TIMING DIAGRAM
CLK
ADSP\
ADSC\
CEx\
CE2
ZZ
IDD
tZZS
tZZREC
IDDzz
AS5SP128K36
Rev. 1.6 10/13
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AS5SP128K36.PDF ] | |
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